1. Computer Engineering Department Research Profile Dr. Sadiq M. Sait Computer Engineering Department King Fahd University of Petroleum & Minerals Dr. Sadiq M. Sait Computer Engineering Department King Fahd University of Petroleum & Minerals

2. Computer Engineering Faculty n 20 Professorial Rank faculty members 2 Full Professor 2 Associate Professor 16 Assistant Professor n 6 lecturers n 20 Professorial Rank faculty members 2 Full Professor 2 Associate Professor 16 Assistant Professor n 6 lecturers

3. COE Research Areas n Data Communications & Computer Networks. n Computer Applications: Robotics, Interfacing, Data acquisition, Machine learning, Data Mining. n Digital Design Automation & VLSI System Design & Test. n Computer Architecture & Parallel Processing. n Computer Arithmetic & Cryptography. n Data Communications & Computer Networks. n Computer Applications: Robotics, Interfacing, Data acquisition, Machine learning, Data Mining. n Digital Design Automation & VLSI System Design & Test. n Computer Architecture & Parallel Processing. n Computer Arithmetic & Cryptography.

4. COE Recent Research Projects: Data Communications & Computer Networks n Wireless Multi-hop Voice over IP over Wi-Fi using Client-Server UDP (user datagram protocol). n Mobile Patient using sensor network. n Wireless Local Area Networks Integration for Mobile Networks Operators. n eTourism Promoter – An Internet Assisted Location Tracker and Map Reader for Tourists. n A Framework for Integration of Web-based Network Management and Management by Delegation. n Radio Resource Management and QoS Control for Wireless Integrated Services Networks. n Adaptive TCP Mechanisms for Wireless Networks. n Engineering Modern Iterative Heuristics to Solve Hard Computer Network Design Problems. n Wireless Multi-hop Voice over IP over Wi-Fi using Client-Server UDP (user datagram protocol). n Mobile Patient using sensor network. n Wireless Local Area Networks Integration for Mobile Networks Operators. n eTourism Promoter – An Internet Assisted Location Tracker and Map Reader for Tourists. n A Framework for Integration of Web-based Network Management and Management by Delegation. n Radio Resource Management and QoS Control for Wireless Integrated Services Networks. n Adaptive TCP Mechanisms for Wireless Networks. n Engineering Modern Iterative Heuristics to Solve Hard Computer Network Design Problems.

5. COE Recent Research Projects: Computer Applications n Design of a wireless safety system for smart kitchen. n Predicting log properties from seismic data using abductive networks. n Design of an Intelligent Tele-robotic System. n Designing and building a mobile emergency warning system for patients under health care. n Context aware energy management system. n Design of a wireless safety system for smart kitchen. n Predicting log properties from seismic data using abductive networks. n Design of an Intelligent Tele-robotic System. n Designing and building a mobile emergency warning system for patients under health care. n Context aware energy management system.

6. COE Recent Research Projects: Design Automation & VLSI System Design & Test. n Iterative Heuristics for Timing & Low Power VLSI Standard Cell Placement. n Parallelization of Iterative Heuristics for Low Power VLSI Standard Cell Placement. n Efficient Test Relaxation Based Static Test Compaction Techniques for Combinational and Sequential Circuits. n Efficient Test Data Compression Techniques for Testing Systems-on-Chip. n Segmented Addressable Scan Architecture for Effective Test Data Compression. n Iterative Heuristics for Timing & Low Power VLSI Standard Cell Placement. n Parallelization of Iterative Heuristics for Low Power VLSI Standard Cell Placement. n Efficient Test Relaxation Based Static Test Compaction Techniques for Combinational and Sequential Circuits. n Efficient Test Data Compression Techniques for Testing Systems-on-Chip. n Segmented Addressable Scan Architecture for Effective Test Data Compression.

7. COE Recent Research Projects: Design Automation & VLSI System Design & Test. n Development of Digital Circuit Techniques for Clock Recovery and Data Re-Timing for High Speed NRZ Source-Synchronous Serial Data Communications. n Fast context switching configurable architectures supporting dynamic reconfiguration for computation intensive applications. n Development of Integrated Micro-electronic Heavy Metal Sensors for Environmental Applications. n Multi-objective Finite State Machine Encoding using Non-Deterministic Evolutionary Algorithms targeting area, low power and testability. n Design and Implementation of Scalable Interconnect Efficient LDPC Error Correcting Codes. n Development of Digital Circuit Techniques for Clock Recovery and Data Re-Timing for High Speed NRZ Source-Synchronous Serial Data Communications. n Fast context switching configurable architectures supporting dynamic reconfiguration for computation intensive applications. n Development of Integrated Micro-electronic Heavy Metal Sensors for Environmental Applications. n Multi-objective Finite State Machine Encoding using Non-Deterministic Evolutionary Algorithms targeting area, low power and testability. n Design and Implementation of Scalable Interconnect Efficient LDPC Error Correcting Codes.

8. Parallelizing Non-Deterministic Iterative Heuristics to Solve VLSI CAD Problems n CAD Problems such as Floorplanning, Placement, Routing, Scheduling, etc., require an enormous amount of computation time. n Iterative Heuristics such as Genetic Algorithms, Tabu Search, Simulated Evolution, and others have been found effective in solving several NP-hard optimization problems. n Objective: To use a cluster of PCs to solve multi- objective VLSI CAD problems in order to improve quality and reduce run-time. n CAD Problems such as Floorplanning, Placement, Routing, Scheduling, etc., require an enormous amount of computation time. n Iterative Heuristics such as Genetic Algorithms, Tabu Search, Simulated Evolution, and others have been found effective in solving several NP-hard optimization problems. n Objective: To use a cluster of PCs to solve multi- objective VLSI CAD problems in order to improve quality and reduce run-time.

9. Approach: To employ a Cluster of PCs to Distribute Computationally Intensive Tasks n Clusters of low end PCs are easy to build. n Tools such as MPI and PVM are available for message passing. n Tools such as gprof, Intel’s VTUNE Performance Analyzer, etc., are used for generating profiles for serial codes and determining the part of the code that has the bottlenecks. n Iterative algorithms are non-deterministic, and dividing work load, i.e. partitioning the search space, is a challenge. n The parallelizing model (i.e., Partitioning, Communication, Agglomeration and Mapping) is very well-defined for numerical problems, which are mostly deterministic. This is not the case for Iterative heuristics, which are non-deterministic. n Clusters of low end PCs are easy to build. n Tools such as MPI and PVM are available for message passing. n Tools such as gprof, Intel’s VTUNE Performance Analyzer, etc., are used for generating profiles for serial codes and determining the part of the code that has the bottlenecks. n Iterative algorithms are non-deterministic, and dividing work load, i.e. partitioning the search space, is a challenge. n The parallelizing model (i.e., Partitioning, Communication, Agglomeration and Mapping) is very well-defined for numerical problems, which are mostly deterministic. This is not the case for Iterative heuristics, which are non-deterministic.

10. Tools used in our Current Cluster n MPICH Library provides a flexible implementation of MPI for easier message-passing interface development on multiple network architectures. n Intel® Trace Collector 5.0 applies event-based tracing in cluster applications with a low-overhead library. Offers performance data, recording of statistics, multi-threaded traces, and automatic instrumentation of binaries on IA-32. n Intel® Trace Analyzer 4.0 provides visual analysis of application activities gathered by the Intel Trace Collector. n TotalView (MPICH) is also used for observing communication between processors. n Also used in Condor (for scheduling jobs on the cluster). n MPICH Library provides a flexible implementation of MPI for easier message-passing interface development on multiple network architectures. n Intel® Trace Collector 5.0 applies event-based tracing in cluster applications with a low-overhead library. Offers performance data, recording of statistics, multi-threaded traces, and automatic instrumentation of binaries on IA-32. n Intel® Trace Analyzer 4.0 provides visual analysis of application activities gathered by the Intel Trace Collector. n TotalView (MPICH) is also used for observing communication between processors. n Also used in Condor (for scheduling jobs on the cluster).

11. Relationship to Intel’s R&D n COE Department has faculty experienced in VLSI Design. n Two books in the area of iterative algorithms and VLSI Design have been authored by the department faculty. n The Technology Center being proposed in RI will have the state-of-art tools and equipment. n Faculty and students currently interested in HPC and parallelization of heuristics can work together to address industrial and real-world problems. n COE Department has faculty experienced in VLSI Design. n Two books in the area of iterative algorithms and VLSI Design have been authored by the department faculty. n The Technology Center being proposed in RI will have the state-of-art tools and equipment. n Faculty and students currently interested in HPC and parallelization of heuristics can work together to address industrial and real-world problems.

12. Efficient Test Compaction & Compression Techniques for Comb. & Seq. Circuits n SOC Testing Challenges Reduce amount of test data. Reduce time a defective chip spends on a tester. n Test Compaction & Compression Reduce the size of a test set as much as possible. n Test vector reordering for combinational circuits. Steepen the curve of fault coverage vs. number of test vectors. n SOC Testing Challenges Reduce amount of test data. Reduce time a defective chip spends on a tester. n Test Compaction & Compression Reduce the size of a test set as much as possible. n Test vector reordering for combinational circuits. Steepen the curve of fault coverage vs. number of test vectors.

13. Efficient Test Compaction & Compression Techniques for Comb. & Seq. Circuits n Efficient Test Relaxation for Combinational & Sequential circuits Enabling technology for test Compaction & Compression Test power reduction n Developed efficient test compaction techniques based on test relaxation. n Test Vector Decomposition Maximizes test compaction by vector clustering techniques Maximizes test width-based compression techniques. n Efficient Test Relaxation for Combinational & Sequential circuits Enabling technology for test Compaction & Compression Test power reduction n Developed efficient test compaction techniques based on test relaxation. n Test Vector Decomposition Maximizes test compaction by vector clustering techniques Maximizes test width-based compression techniques. 110011001 011000110 000110011 101111100 000010001 1X0XX100X X11XX0X10 0XXXX0XX1 XXXX111XX X0X01XXXX Test Relax. 110011001 X1XXX1X0X XXX00XXX1 1XXX1X0XX

14. Segmented Addressable Scan: Scan Test Challenges n Test data volume challenge Limited IOs & unlimited increase in transistors Exponential increase in test data volume n Tester pin count challenge Tester cost is almost linear in number of pins n Test time challenge Critical path Hard to parallelize test loading massively n Test power challenge High activity leading to high power consumption. n Test data volume challenge Limited IOs & unlimited increase in transistors Exponential increase in test data volume n Tester pin count challenge Tester cost is almost linear in number of pins n Test time challenge Critical path Hard to parallelize test loading massively n Test power challenge High activity leading to high power consumption.

15. Segmented Addressable Scan  Aggressive parallelization of scan chains  Reconfigurable partial compatibilities  Special SAS decoder  Overhead: few gates per scan chain  Data volume: 10x ~ 20x compression with small designs for both SAF and TDF Bigger designs have higher compression  Pin count: 2  log 2 S  +1 pins, can be reduced to ONLY 2  Test time: aggressive parallelization  test time reduction  Power consumption selective clocking

16. Test Data Volume & Test Time (Delay test) Total Data Volume98 MbCompression Ratio SAS Data Volume 32 Segments 7.7 Mb12x 64 Segments 5.3 Mb17x 128 Segments 4.5 Mb22x 256 Segments 3.6 Mb27x $Ms of annual test cost savings

17. COE Recent Research Projects: Computer Architecture & Parallel Processing n Load Balancing for Parallel Visualization of Blood Head Vessel Angiography on Cluster of PCs. n Shared Channels in Interconnection Networks. n Study of modified Multistage Interconnection Networks for Networks-on-Chips. n Design of a Simulator for a Class of Dynamic Execution Processors. n Beyond Instruction-Level Parallelism in Processor Architecture. n Design and Performance Evaluation of a Distributed Crossbar Scheduler. n Software Pipelining for Reconfigurable Instruction Set Processors. n Load Balancing for Parallel Visualization of Blood Head Vessel Angiography on Cluster of PCs. n Shared Channels in Interconnection Networks. n Study of modified Multistage Interconnection Networks for Networks-on-Chips. n Design of a Simulator for a Class of Dynamic Execution Processors. n Beyond Instruction-Level Parallelism in Processor Architecture. n Design and Performance Evaluation of a Distributed Crossbar Scheduler. n Software Pipelining for Reconfigurable Instruction Set Processors.

18. COE Recent Research Projects: Computer Arithmetic & Cryptography n High-Performance Arithmetic for Cryptographic Applications. n Design of efficient integrated circuits for the inverse computation in different finite fields. n Design of Elliptic Curve Cryptography Architectures using parallel multipliers. n Secure reliable storage system. n Design, Analysis, and FPGA prototyping of High- Performance Arithmetic for Cryptographic Applications. n High-Performance Arithmetic for Cryptographic Applications. n Design of efficient integrated circuits for the inverse computation in different finite fields. n Design of Elliptic Curve Cryptography Architectures using parallel multipliers. n Secure reliable storage system. n Design, Analysis, and FPGA prototyping of High- Performance Arithmetic for Cryptographic Applications.

19. Computer Engineering Faculty Research Profile