1. An Ion-Trap Microarchitecture for Quantum Computation Tzvetan S. Metodi, Darshan D. Thaker, and Frederic T. Chong University of California QARC Quantum Architecture Research Center Andrew W. Cross and Isaac L. Chuang Massachusetts Institute of Technology 

2. The Quantum Architecture Research Center QARC Quantum Architecture Research Center  Mark Oskin John Kubiatowitz Isaac Chuang Fred T. Chong

3. Quantum Computers Today Complexity (# gates) # of quantum bits 1234567 98 00 01 03 99,01 98 99 QARC NMR Supercond. Ion Trap 99, Oxford 03, NEC 00, Frankfurt 01, LANL 00, LANL 99, Cambridge 99,00, MIT 00 98, LANL 00 00, NEC 99, Oxford 00, NIST 02, NIST /Saclay Delft / UK 03 Ion trap DJ 96, NIST FACTORING (NMR) 01, NIST 04, NIST

4. 10 5 qubits 10 6 gates Factor 1024-bit Number Our Goal … Factor 2048-bit Number 10 7 gates 10 6 qubits

5. Building a Quantum Architecture Reliable and Realistic Technology Reliable and Realistic Technology Reliable initialization Reliable initialization Universal set of quantum operations Universal set of quantum operations Ability to Measure the system Ability to Measure the system Fault-Tolerant Structures and Error Correction Fault-Tolerant Structures and Error Correction Efficient Quantum Resource Distributions. Efficient Quantum Resource Distributions.

6. Brief Talk Outline The Ion-Trap Technology The Ion-Trap Technology Quantum Logic Array (QLA) overview Quantum Logic Array (QLA) overview Communication Mechanism Communication Mechanism Example (FT Toffoli Gate) Example (FT Toffoli Gate) Numerical Results and Conclusion Numerical Results and Conclusion

7. Trapped Ions for Quantum Computation Cirac and Zoller in 95’. A number of atomic ions trapped in a linear RF trap that interact with Lasers beams to quantum compute. electrode ion (Be + ) aluminum substratelaser segmented RF Paul Traps

8. Single-Trap Example

9. Trapped Ions for Quantum Computation Mg + cooling laser Lasers implement logic gates and measurement, where multi-qubit gates are implemented using the vibrational modes of multiple ions coupled in a linear chain. Sympathetic Recooling ions are needed to reduce the vibrational heating, which affects the gate fidelity data ion Cirac and Zoller in 95’. A number of atomic ions trapped in a linear RF trap that interact with Lasers beams to quantum compute. electrode ion (Be + ) aluminum substratelaser segmented RF Paul Traps

10. Array of Linear Traps allow scalability by limiting the number of ions per trap. Quantum communication via ballistic transport from the memory region to the interaction region. Ions are moved by changing trapping voltages. Kielpinski et al, Nature v417, p 709, 2002 QCCD: Quantum Charge Coupled Device our abstraction Original QCCD

11. Error-Correction Example

12. Data Ions Quantum Channels Electrodes Cooling Ions QLA design trades area for communication to provide both scalability and flexibility for large-scale fault- tolerant architectures Basic Blocks: Each building block consists of electrodes, the data ion, the sympathetic cooling ion, and free space around it to allow for the building of channels when the basic blocks are tiled together. Fault-Tolerant Structures: Large-scale fault-tolerant architectures can be built by tiling basic blocks to form logical qubits and interconnect channels between them. Qubit structures are built at design-time with computations mapped at run-time. Basic Building Block Quantum Logic Array (QLA): a reconfigurable microarchitecture

13. High Level Architecture Overview Classical Control Processors Logical Qubit RR Logical Qubit R Logical Qubit R Logical Qubit R Logical Qubit R Classical Control Processors Sea of lowerlevelqubits Channel Channel R QLA Building Tile Average physical gate failure rates are assumed to be ~10 -7 with cell size of 20 by 20 microns.

14. High Level Architecture ~100 logical qubits per 90nm-technology Pentium 4 processor, compared to 55 million classical transistors within each such P4 Classical Control Processors Logical Qubit RR Logical Qubit R Logical Qubit R Logical Qubit R Logical Qubit R Classical Control Processors 49 Physical Ions--- 5292 trap cells 720 μm 2940 2.11 mm 2

15. Q1 Qk 256 qubits ~ 30,000 cells EPR Ballistic channels are too faulty for the data to move through at very large distances. We use the concept of teleportation developed by Bennet et. al. in 93, which employs entangled EPR pairs to recreate the state of an ion at the desired destination without physically moving the ion. The EPR pairs are purified upon arrival with the use of ancillary EPR pairs, which are constantly reinitialized to zero. Inter-Qubit Communication source destination

16. Q1 Qk EPR pair RR Quantum Repeaters source destination RRRR R RR

17. Q1 Qk EPR pair RR

18. Quantum Repeaters Q1 Qk EPR pair RR

19. Quantum Repeaters Q1 Qk EPR pair RR Next: Channel Detail Teleporting the data

20. Communication Channel: Detail Purify Initialize EPRPurify Initialize Repeater ion

21. Communication Channel: Detail Purify Initialize EPRPurify Initialize Repeater ion 0.2 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 Total Connection Time d=35 d=70 d=100 d=500 d=750 d=1000 d=100 Separation Distance (d) d=350 350 700 1750 3500 7000 10500 20000 Total Communication Distance (cells)

22. Simple Example: Toffoli Gate X Y Z X Y Zxor XY Discovered by Toffoli in 1981, the Toffoli Gate is a controlled-controlled-NOT gate. This gate is a universal gate for reversible computation and is a special case for the three bit universal gate for quantum logic. The NAND gate is contained within the Toffoli X Y 1 X Y X nand Y Toffoli

23. Fault-Tolerant Toffoli Gate Construction

24. Simple Example (FT Toffoli Gate) Data anc A0A1A2 XY Z C0C1C2 Heuristic Greedy Scheduler that grabs all available bandwidth whenever it can. Goal is to find the minimum number of paths and bandwidth between logical qubits such that communication and computation can be overlapped.

25. A0A1A2 XY Z C0C1C2 Move A2 --> C2 FT Toffoli Scheduler …

26. A0A1 A2 XY Z C0C1 C2 A2 Move C2 --> A1 Move A2 --> C1 FT Toffoli Scheduler …

27. 3 ancilla preparations + data interaction = 3*16 + 5 = 53 ECC cycles. At 0.043 seconds per ECC cycle at level 2, we have ~2.5 seconds per Toffoli gate. FT Toffoli (Numerical Estimations) RR RRR R R R RR RRR R R R RR RRR R R R RR RRR R R R

28. Factoring an Integer (RSA) ModularExponentiation QFT Period of f(x) Classical Post processing Toffoli Classical Factoring: Exponential complexity. Cavallar in 2000 has demonstrated the factorization of a 512-bit number in seven calendar months on 300 fast workstations, two SGI Origin 2000 computers, and one Cray C916 Supercomputer - a process which amounts to 8400 MIPS years. Quantum Factoring: Shor’s Algorithm proposes polynomial time, however real time estimates currently don’t exist due to the complexity of the system.

29. Factoring an Integer 128-bit: 63,730 Toffoli Gates with 21 ECC steps per Toffoli for modular exponentiation. Thus we have 21(63,730)+QFT = 1.34 x 10 6 time steps = ~ 16 hours.  16*1/.75  ~21 hours 128-bit: 63,730 Toffoli Gates with 21 ECC steps per Toffoli for modular exponentiation. Thus we have 21(63,730)+QFT = 1.34 x 10 6 time steps = ~ 16 hours.  16*1/.75  ~21 hours 512-bit: 397.910 Toffoli Gates + QFT  ~5.5 days 512-bit: 397.910 Toffoli Gates + QFT  ~5.5 days 1024-bit: 964,919 Toffoli Gates + QFT  ~13.4 days 1024-bit: 964,919 Toffoli Gates + QFT  ~13.4 days 2048-bit: 2,301,767 Toffoli Gates + QFT  ~32 days 2048-bit: 2,301,767 Toffoli Gates + QFT  ~32 days ModularExponentiation QFT Period of f(x) Classical Post processing

30. Multi-Chip Area Solution QQQQ QQQQ QQ BS D1 D2 Single Chip Laser Beams Optical Fiber Imaging Lens ION To Next Chip + Two ion-trap chips are connected through an optical fiber network, where collected photons into a Beam Splitter (BS) station from two remote ions are measured forcing the ions into an entangled state. After the entanglement procedure we can teleport data ions from one chip to the next.

31. Laser Limitations Current lasers are the size of room! Current lasers are the size of room! Expect ~6-12 lasers Expect ~6-12 lasers Distribute with MEMS mirror Distribute with MEMS mirror

32. MEMS Mirror Array

33. SIMD Control Many mirrors but few lasers -> similar to Single Instruction Multiple Data computers Many mirrors but few lasers -> similar to Single Instruction Multiple Data computers Limits to parallelism -> longer computation -> more error correction -> more control (!) Limits to parallelism -> longer computation -> more error correction -> more control (!)

34. Future Work Scheduler to optimize execution time and number of lasers Scheduler to optimize execution time and number of lasers Compiler to minimize data lifetimes Compiler to minimize data lifetimes Traditionally, maximal parallelism minimizes data lifetimes implicitly by minimizing execution time Traditionally, maximal parallelism minimizes data lifetimes implicitly by minimizing execution time Goal: explicitly minimize data lifetime and reduce parallelism to reduce machine size Goal: explicitly minimize data lifetime and reduce parallelism to reduce machine size

35. Future Work (2) Decoherence-Free Subspaces Decoherence-Free Subspaces Error correction assumes uncorrelated errors Error correction assumes uncorrelated errors Pair ions and use difference to represent data -> cancels out correlated errors Pair ions and use difference to represent data -> cancels out correlated errors

36. Qubits are phosphorus atoms in silicon Control with classical wires Silicon Device Technology [Skinner+02]

37. Fundamental Constraint: Quantum gates require classical control lines! Quantum: 20 nm Classical: 100’s of nm ( Marcus 1997 ) ( Nakamura, Nature 398, p. 786, ‘99 )( Yablonovitch, 1999 )

38. Quantum vs. Classical What if transistors were 3 orders of mag. smaller than wires [Isailovic et al ACM TACO 2003]

39. Architectural Implications Communication is critical

40. A simple quantum wire Short wire constructed from swap gates –Each step requires 3 CNOT ops (swap) Key difference from classical: –qubits are stationary

41. How far can you communicate? This is a show stopper log(1 - C)/-λ lat = T x D bw = 1/T e -λD T = time per swap D = distance (bits) λ = error rate Latency Bandwidth

42. Recursive Structures

43. Control Pulse Sequence 2-D layout (mentioned in Kane ’00) moves electrons in parallel –Simpler control –Better electron separation Control signals still complicated! –S-gate cascade –A-gate sequence

44. Swap control circuit Off-on A-gate pulse subsequence (2 off, 254 on)A-gate pulse repeats 24 times S-gate pulse cascade

45. Large! Control circuit area, ~10um 2 –Aggressive process, 30nm feature size –Minimal design Swap cell area, ~0.068um 2

46. SIMD Control Large control circuit/small swap cell ratio = SIMD [Isailovic et al ACM TACO 2003]

47. Clustering Recursive scheme is overkill Don’t error correct every operation [Oskin,Chong,Chuang IEEE Computer 02]

48. Space Savings Shor’s Grover’s p=10 -6

49. Time Savings Shor’s Grover’s p=10 -6

50. Building Block (I) Measurement unit – computational & Bell basis Measure Qubit to measure Zero qubit Classical control Classical {0,1} output with probability determined by 

51. Building Block (II) EPR generation unit EPR EPR Generator Zero qubits Classical control Quantum output of an EPR state

52. Building Block (III) Entropy exchange unit … EX P Polarized Light Polarized Electrons Electric Field Ground

53. Building Block (IV) Purification unit – error correction Pur Purification Unit EPR states to purify Classical control Purified EPR states Zero bits Garbage state (to Entropy Exch)

54. General-Purpose Architecture Teleportation connects comp. units Self-refreshing memory Parallel quantum ALU Classical microprocessor control Dynamic compilation Scheduling Classical Microprocessor Spin Polarized Electrons Qubits Pur EPR EX Classical Bus Quantum Bus