1. On-Chip Interconnect Analysis and Evaluation of Delay, Power, and Bandwidth Metrics under Different Design Goals

2. Introduction Interconnect strategy, or interconnect planning has become a critical part of chip design: the growing significance of wire delay relative to gate delay. increasing power consumption of wires: could be up to 50% of the total dynamic power. Influences the ASIC design methodology

3. Our work Try to revamp the on-chip local interconnect configuration for multi-objective optimization: –Compare different objective functions. –Formulate various matrics to measure the wire performance. –Identify the optimal wire configurations.

4. Evaluation Approach and Models objective functions: – – is the wire-length normalized delay. – is the wire-length-normalized power.

5. Evaluation Approach and Models Metrics –is amount of data that can be transferred per unit area per unit time.

6. Evaluation Approach and Models Models –Elmore delay model: –Power model: –Leakage factor:

7. Minimum Delay Optimum repeater interval and size: Optimum delay and power

8. Experimental results: wire configuration Optimal inverter sizesOptimal widths

9. Optimal inverter distances in the min-dp procedure Optimal inverter distances in the min-ddp procedure Optimal inverter distances in the min-d procedure

10. Experimental results: metric evaluation