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CENG 241 Digital Design 1 Lecture 9 Amirali Baniasadi

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Presentation on theme: "CENG 241 Digital Design 1 Lecture 9 Amirali Baniasadi"— Presentation transcript:

1 CENG 241 Digital Design 1 Lecture 9 Amirali Baniasadi amirali@ece.uvic.ca

2 2 This Lecture zReview of last lecture zJK, T Flip-Flops zDirect Inputs, Analysis of Clocked Sequential Circuits

3 3 Graphic Symbols

4 4 Other Flip-Flops zEach flip-flop is made of interconnection of gates. zThe edge-triggered D flip-flop is the most efficient flip-flop since it requires the least number of gates. zOther flip-flops are made using the D flip-flop and extra logic. zTwo flip-flops widely used are the JK and T flip-flop.

5 5 JK Flip-Flop zThree flip-flop operations: Set, Reset, Complement output. zJK performs all three

6 6 D = JQ’ + K’Q if J=1, K=0 then D=Q’+Q=1 if J=0, K=1 then D=0 if j =1, K=1 then D = Q’ JK Flip-Flop

7 7 T Flip-Flop T (Toggle) flip-flop is a complementing one. T flip-flop is obtained from a JK when inputs J and K are tied together.

8 8 T Flip-Flop If T=0 ( J=K=0) output does not change. If T=1 ( J=K=1) output is complemented. A T flip-flop can also be made of D flip-flop and a XOR. D = T XOR Q = TQ’ + T’Q

9 9 Characteristic Tables zJK Flip-flop zJ K Q(t+1) z0 0 Q(t) No change z0 1 0 Reset z1 0 1 Set z1 1 Q’(t) Complement

10 10 Characteristic Tables zD Flip-flop zD Q(t+1) z0 0 Reset z1 1 Set zT Flip-flop zT Q(t+1) z0 Q(t) No change z1 Q’(t) Complement

11 11 Direct Inputs Some flip-flops have asynchronous inputs to force the flip-flop to a particular state. Examples: Direct Set, Direct Reset. The input that sets the flip-flop to 1 is called preset or direct set. The input that clears the flip-flop to 0 is called clear or direct reset. Works independent of clock.

12 12 Direct Inputs: Asynchronous Reset When reset is 0, Q’ is forced to 1.

13 13 zAnalysis: Obtaining a table/diagram for the time sequence of inputs/outputs/internal states. zExamples: State Equations, State Table, State Diagram Analysis of Clocked Sequential Circuits

14 14 Analysis of Clocked Sequential Circuits Example of state equation: A(t+1) = A(t)x(t) + B(t)x(t) B(t+1) = A’(t)x(t) A(t+1)=Ax+Bx B(t+1)=A’x y(t)=(A(t)+B(t)).x’(t) = (A+B)x’

15 15 Example of state tables zPresent state input Next State Output zA B x A B y z0 0 0 0 0 0 z0 0 1 0 1 0 z0 1 0 0 0 1 z0 1 1 1 1 0 z1 0 0 0 0 1 z1 0 1 1 0 0 z1 1 0 0 0 1 z1 1 1 1 0 0 State equation: A(t+1) = A(t)x(t) + B(t)x(t) B(t+1) = A’(t)x(t) y(t)=(A(t)+B(t)).x’(t)

16 16 Example of state tables-2nd form zPresent state Next State Output z x=0 x=1 x=0 x=1 zAB AB AB y y z00 00 01 0 0 z01 00 11 1 0 z10 00 10 1 0 z11 00 10 1 0 State equation: A(t+1) = A(t)x(t) + B(t)x(t) B(t+1) = A’(t)x(t) y(t)=(A(t)+B(t)).x’(t)

17 17 Example of state diagram Present state Next State Output x=0 x=1 x=0 x=1 AB AB AB y y 00 00 01 0 0 01 00 11 1 0 10 00 10 1 0 11 00 10 1 0

18 18 Analysis- D flip-flop

19 19 Analysis: JK flip-flop J A =B K A =Bx’ J B =x’ K B =A’x+Ax’

20 20 Analysis: JK flip-flop A(t+1)=JA’+K’A B(t+1)=JB’+K’B A(t+1)=BA’+(Bx’)’A=A’B+AB’+Ax B(t+1)=x’B’+(A XOR x’)B =B’x’+ABx+A’Bx’

21 21 Analysis: JK flip-flop Present state input Next State A B x A B 0 0 0 0 1 0 0 1 0 0 0 1 0 1 1 0 1 1 1 0 1 0 0 1 1 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1

22 22 Analysis: T flip-flop Q(t+1)=T’Q+TQ’ T A =Bx T B =x y=AB A(t+1)=(Bx)’A+(Bx)A’ =AB’+Ax’+A’Bx B(t+1)=x XOR B

23 23 Summary zAnalysis zReading up to page 214


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