1. Cascading CMOS gates

2. Elettronica T A.A. 2010-2011 Digital Integrated Circuits © Prentice Hall 2003 Cascading CMOS Goal l Designing for minimum propagation delay: Fixed number of stages Optimum number of stages

3. Elettronica T A.A. 2010-2011 Digital Integrated Circuits © Prentice Hall 2003 Cascading CMOS Example 1:Two cascaded inverters S=W/L CL/Ci=  Ip: Cp= Cin(Inv2) Inv2 Inv1 Cp= u Ci SSuSuS uS Cp CL ViVpVo

4. Elettronica T A.A. 2010-2011 Digital Integrated Circuits © Prentice Hall 2003 Cascading CMOS Transistor sizing two cascading stages: minimize propagation delay: Vi Vp (u) Vo Ci Cp CL I B

5. Elettronica T A.A. 2010-2011 Digital Integrated Circuits © Prentice Hall 2003 Cascading CMOS Example Two stages are faster than one if:

6. Elettronica T A.A. 2010-2011 Digital Integrated Circuits © Prentice Hall 2003 Cascading CMOS Sizing Logic Paths for Speed l Frequently, input capacitance of a logic path is constrained l Logic also has to drive some capacitance l Example: ALU load in an Intel’s microprocessor is 0.5pF l How do we size the ALU datapath to achieve maximum speed? l We have already solved this for the inverter chain – can we generalize it for any type of logic?

7. Elettronica T A.A. 2010-2011 Digital Integrated Circuits © Prentice Hall 2003 Cascading CMOS Delay in a Logic Gate Gate delay: d = h + p effort delay intrinsic delay Effort delay: h = g f logical effort effective fanout = C out /C in Logical effort is a function of topology, independent of sizing Effective fanout (electrical effort) is a function of load/gate size

8. Elettronica T A.A. 2010-2011 Digital Integrated Circuits © Prentice Hall 2003 Cascading CMOS Optimum number of stages: buffer Why a buffer - long interconnection wires - chip interfaces

9. Elettronica T A.A. 2010-2011 Digital Integrated Circuits © Prentice Hall 2003 Cascading CMOS Chip interface: an example Pentium (7 buffer) L = (10.2-19.9) nH Cp = (2.6 - 9.7) pF Co = (4.8 -17.1) pF PADPIN CoCp L

10. Elettronica T A.A. 2010-2011 Digital Integrated Circuits © Prentice Hall 2003 Cascading CMOS Long interconnection wires

11. Elettronica T A.A. 2010-2011 Digital Integrated Circuits © Prentice Hall 2003 Cascading CMOS Single interconnection capacitance

12. Elettronica T A.A. 2010-2011 Digital Integrated Circuits © Prentice Hall 2003 Cascading CMOS Total interconnection capacitance

13. Elettronica T A.A. 2010-2011 Digital Integrated Circuits © Prentice Hall 2003 Cascading CMOS Example: 2 inverter stages F Too large !

14. Elettronica T A.A. 2010-2011 Digital Integrated Circuits © Prentice Hall 2003 Cascading CMOS Multiple stage Buffer VGVG C1C2 C N-1 CL Vi V1 V2Vo 1 2 3 N u u2u2 u N-1

15. Elettronica T A.A. 2010-2011 Digital Integrated Circuits © Prentice Hall 2003 Cascading CMOS Cascading CMOS inverters Minimizing tp:

16. Elettronica T A.A. 2010-2011 Digital Integrated Circuits © Prentice Hall 2003 Cascading CMOS Propagation delay vs sizing factor u

17. Elettronica T A.A. 2010-2011 Digital Integrated Circuits © Prentice Hall 2003 Cascading CMOS Example CMOS 1  m; Ci=10fF; tp 0.2ns CL=20pF X= 2000 7 stages tp 4ns Stage 1 2 3 4 5 6 7 Wn(  m) 1.8 5.3 15.8 47.7 138.2 409.9 1210.7 Wp(  m) 2.8 8.4 24.9 73.8 218.3 646.21912.8

18. Elettronica T A.A. 2010-2011 Digital Integrated Circuits © Prentice Hall 2003 Cascading CMOS Tri-State CMOS Buffer