1. FM Transmitter

2. FM Modulation using VCO V in f out - Gain of VCO - Free Running Frequency of VCO Corresponding DC bias [1]

3. Block Diagram DC Bias Vcc/2  VCO PA Input

4. Chipset 4046 Phase-Locked Loop LM7171 Wide-Band Power Amplifier 741 Op Amp

5. 4046 PLL Only use the VCO

6. 4046 VCO Characteristic C1>=100pF

7. Schematic

8. PCB Layout Considerations The signal traces should be short and wide to lower the impedance. The width of the signal traces has to satisfy current driving capacity. Any used board area should be shorted to ground to reduce AC noise. Sockets and pads will induce extra capacitance, so components should be directly soldered to board. Surface mount components are preferred over discrete ones for less lead inductance.

9. PCB Layout

10. Measured Results Carrier Frequency: 15MHz Bandwidth: Controllable Output Power: 500mW

11. FM Receiver

12. FM Demodulation using PLL PFDLF VCO VeVe  in [2]

13. Loop Filter Design [3]

14. VCO Design VCO free running frequency = Carrier Frequency VCO Frequency Range is no smaller than Bandwidth Large VCO gain will increase PLL natural frequency  n and thus improves PLL tracking capability

15. Block Diagram LNA PFDLF VCO Amp BPF

16. Chipset 4046 PLL CLC425 Wide-band LNA

17. 4046 PLL

18. Schematic

19. PCB Layout

20. Superheterodyne FM Receiver

21. Block Diagram Amp Input Matching Mixer IF Amp + IF Filter LO FM Demodulator

22. Chipset TDA7000 – FM Radio LM3875 – Audio Power Amplifier

23. TDA7000 [4]

24. IF Filter

25. Quadrature Demodulator f in V out

26. IF Harmonic Distortion IF=70kHz

27. IF Distortion Suppression FLL

28. Correlator To suppress interstation noise Not Modulated Lightly Modulated Heavily Modulated

29. Schematic

30. PCB Layout

31. Monolithic FSK Transmitter [5]

32. Block Diagram A/D Converter Shift Register PLL Dual Modulus Prescaler Analog Input Reference Frequency Output ClockData Sampling Rate Digital Input

33. Inverter

34. NAND – 2 Input

35. NAND – 3 Input

36. NAND – 4 Input

37. NOR – 2 Input

38. XOR

39. Transmission Gate

40. Edge-Triggered D Flip-Flop

41. D Flip-Flop with ‘CLEAR’

42. Voltage Comparator

43. 8-to-3 Encoder

44. A/D Converter

45. Parallel-Serial Shift Register

46. Phase-Frequency Detector

47. VCO

48. Dual Modulus Prescaler [6]

49. Output Driver To drive capacitive load with minimum delay

50. Capacitor Driving Capability C L =100p f=50MHz

51. Synthesizer

52. Synthesizer Response

53. ADC and SR Response

54. Chip Layout

55. Digital Switching Noise [7]

56. Noise Mechanism Digital switching injects current into substrate through various kinds of capacitance, which propagates through the substrate and affects analog circuits. Digital switching draws current from power supply rail with impedance and thus creates voltage drop on power supply rail.

57. Digital Switching Noise in PLL PLL is a typical mixed-signal integrated circuit PFDLFVCO /N Noise Coupling

58. Simulation Results Error Voltage VCO output

59. Noise Reducing Techniques Use Differential Topology Separate Power Supply Rails Use guard rings Multi-chip Module Heterogeneous integration

60. Test Structure 1 PFDLFVCO /N All building blocks share power supply rails

61. Chip Layout 1

62. Test Structure 2 PFDLFVCO /N The counter uses separate power supply rails

63. Chip Layout 2

64. Test Structure 3 PFDLFVCO /N The counter uses separate power supply rails The PFD and VCO are shielded and ring guarded

65. Guard Ring p+p+ p+p+ P-type Substrate Sink the coupling

66. On-Chip Shielding Metal 3 ICsVia2 Via1 Contact Ohmic Contact Radiation

67. Chip Layout 3

68. Test Structure 4 PFDLFVCO /N The counter uses separate power supply rails Use guard rings around PFD and VCO Implement LC VCO

69. LC VCO Lower Phase Noise than Ring Oscillator

70. Oscillator Basics - Tank Loss Positive feedback of 2n  phase shift Unity loop gain Phase noise is reverse proportional to Q [8]

71. Chip Layout

72. Electromagnetic Coupling

73. Microstrip Line Coupling L S W 1 2 34 [9]

74. Electric Field Distribution Even Mode Odd Mode

75. Impedance Matrix  - propagation constant Z oe - even mode characteristic impedance Z oo - odd mode characteristic impedance

76. Different Configurations Low Pass Band Pass

77. Experiment Setup

78. Results The coupling depends on L, W, S, and 

79. Integrated Inductor Coupling Coupling between integrated spiral inductors Coupling from spiral inductors to transistors [10]

80. 2.5D Integrated Inductor [11]

81. Interference Effects on PLL Performance [12]

82. References 1.Jerry D. Gibson, Principles of Digital and Analog Communications 2.Floyd M. Gardner, Phaselock Techniques 3.Roland E. Best, Phase-Locked Loops – Theory, Design, and Applications 4.W.H.A. Van Dooremolen and M. Hufschmidt, A complete FM radio on a chip 5.R. Jacob Baker, Harry W. Li, David E. Boyce, CMOS Circuit Design, Layout, and Simulation 6.J. Navarro Soares and W.A.M. Van Noije, A 1.6-GHz Dual Modulus Prescaler Using the Extended True-Single-Phase-Clock CMOS Circuit Technique, IEEE Journal of SSCC, Vol.34, No.1, Jan 1999 7.Patrik Larsson, Measurements and Analysis of PLL Jitter Caused by Digital Switching Noise, IEEE Journal of SSCC, Vol.36, No.7, July 2001 8.Dan H. Wolaver, Phase-Locked Loop Circuit Design 9.E.M.T.Jones and J.T.Bolljahn, Coupled-Strip-Transmission-Line Filters and Directional Couplers, IRE Trans on Microwave Theory and Techniques, 1956 10.A.O.Adan, M.Fukumi, K.Higashi, T.Suyama, M.Miyamoto, M.Hayashi, Electromagnetic Coupling Effects in RFCOMS Circuits, 2002 IEEE MTT-S Digest 11.Jaime Aguilera and Joaquin De No, A Guide for On-Chip Inductor Design in a Conventional CMOS Process for RF Application 12.Murat F. Karsi, William C. Lindsey, Effects of CW Interference on Phase-Locked Loop Performance, IEEE Trans on Comm, Vol.48, No.5, May 2000