1. Design of Microwave Power Amplifier with ADS Technische Universität Berlin Fachgebiet Mikrowellentechnik
Daniel Gruner, Ahmed Sayed, Ahmed Al Tanany, Khaled Bathich,
Henrique Portela, Amin Hamidian, Georg Boeck

2. Outline Introduction PA Overview ADS Design Flow
Power Amplifier Design
 Transistor Characterization
 Hybrid Broadband Power Amplifier
 Hybrid Doherty Power Amplifier
 Hybrid Switch Mode Power Amplifier
 Monolithic 6 GHz Power Amplifier
 Monolithic 24 / 60 GHz Power Amplifier
Summary and Conclusion

3. Microwave Engineering Laboratory, Berlin Institute of Technology
Introduction
Microwave Engineering Laboratory, Berlin Institute of Technology
Research Focus
Hybrid Design
- Power Amplifier (Broadband,
Doherty, Switch Mode…)
- Characterization of passive and active devices
- 10/40 GHz Synthesizer
- Distance measurement system
- Local positioning system
MMIC Design
- Power Amplifier (6 GHz, 24 GHz, 60 GHz…)
- Modeling of passive mm wave structures
- Characterization of integrated devices
- RF front end design (6 GHz, 24 GHz, 60 GHz)

4. PA Overview (1)
Power amplifiers (PAs) belong to the most challenging function blocks in every communication system
PA is the last active part in a transmit system, followed by the transmitting antenna

5. PA Overview (2)
PA design for a huge variety of different standards, frequency bands, power levels, device technologies…
Communication Applications Spectrum
f [MHz]

6. PA Overview (3) Performance Metrics
 Output power: strongly depend. on the load impedance
Efficiency: measure for transformation of DC to RF energy
(PAE, Drain-/Collector-, overall efficiency)
 Linearity: IP3, ACPR, AM-AM/PM-Conversion
 Maximum ratings: guarantee max. temp., voltage, current…
 Less important: Small signal behavior, matching etc.

7. PA Overview (4) Fundamental PA categories  Linear PA
- Classes A, B, AB, C
 Switch Mode PA
- Classes D, D-1, E, F, F-1, S, etc.
 Combinations, extensions, smart transmitters
- Power Combining, Doherty, Chireix, LINC, etc.

8. PA Overview (5)  Conduction angle of 360o  Linear operation
Class A:
 Conduction angle of 360o
 Linear operation
 Low efficiency: PAEMAX = 50% (GP  ∞) RL
VDD
Drive
and
Bias
VGS
IDS Vp
VDS
Load line
Bias point
Imax
Imax/2
VDD
T/4
T/2
3T/4 T
Vknee
VDD
2VDD-Vknee
Voltage [V]
Current
Voltage Iq
Imax
Current [A]

9. PA Overview (6) Class B:  Conduction angle of 180o
 Less linear than class A
 Increased efficiency: PAEMAX = 78.5 %
T/4
T/2
3T/4 T
Current
Voltage
Imax
Vknee
VDD
2VDD-Vknee
Voltage [V]
Current [A]
IDS
IDS
Imax
Bias point VP
VGS
VDS

10. PA Overview (7)  Conduction angle: 180° < Θ < 360°
Class AB:
 Conduction angle: 180° < Θ < 360°
 Compromise between class A and class B
 Trade off between linearity and efficiency I
2VDD-Vknee
Imax DS I
max
Current
Voltage
Voltage [V]
VDD
Current [A]
Class AB
Vknee
T/4
T/2
3T/4 V T V p GS

11. PA Overview (8) Class C:  Conduction angle: Θ < 180°
 Increased efficiency compared to class B
 but: decreased POUT
T/4
T/2
3T/4 T
Vknee
VDD
2VDD-Vknee
Voltage [V]
Current
Voltage
Imax
Current [A] I DS I
max
Class C V V p GS

12. PA Overview (9)
Increased efficiency  Reduced battery / power consumption
 Lower cooling effort & extended active device lifetime
 Reduced volume, weight and cost
Classical classes
- Simultaneous voltage and current
- Dissipation across the device
- Limits practical efficiency
Switch mode classes
- Non-overlapping waveforms
- Dissipated power is low
- High efficiency is enabled
- Linearity is critical A AB SM
IDS
IMAX IQ
VKnee
VDD
2VDD- VKnee
VDS

13. PA Overview (13) Doherty Power Amplifier Efficiency of classical PAs
decreases in back-off region
Critical for modern wireless
standards with high PAR
Solution
 Two PAs connected in parallel
 Main PA (AB) and Peaking PA (C)
 Load modulation
 High efficiency is maintained
in back-off region P
out E f i c e n y
sat
P dB
DPA

14. ADS Design Flow

15. PA Design  Transistor Characterization (1)
Optimized amplifier performance
 Maximization of Pout , efficiency, targeted input power / bias
 Tuning (pulling) of the source and/or load impedance until optimum PA
 Can be performed on simulation
and measurement level

16. PA Design  Transistor Characterization (3)
Eudyna GaN-HEMT, 10 Watt, VDD = 48 V, ID= 120 mA
ZLOAD,OPT @ 2-4 GHz
Load-Pull, 2 GHz
Device Ref. Plane

17. PA Design  Transistor Characterization (4)
Measurement vs. ADS-Simulation, 10 W GaN-HEMT Eudyna
 Good agreement between measurement and simulation
ZOPT
ADS-Simulation
Measurement
ΓSOURCE
ΓLOAD
ADS-Simulation
Measurement
f = (2, 2.5, 3, 3.5, 4) GHz
f = (2, 2.5, 3, 3.5, 4) GHz

18. PA Design  Hybrid Broadband PA (1)
Step 1: PA requirements
Step 2: Transistor selection
Step 3: Load/Source Pulling
Step 4: Networks verification
Step 5: Assembly
 Meas. vs. ADS-Simulation
Pout contours   P1 L1
TL22
C305
C306
C307
C308
C271
C270
C298
C269
DAC1
DAC
Term2
PORT1
TL96
TL3
Tee38
TL97
TL134
TL95
TL98
Tee39
TL94
SNP7
TL4
TL115
Tee45 

19. PA Design  Hybrid Broadband PA (2)
Network verification

20. PA Design  Hybrid Broadband PA (3)
 Example I: 5 W, – 3 GHz PA
Transistor: GaN-HEMT, Cree (packaged)
BW [GHz]
0.001 – 3
Gain [dB] 12
OP1dB [dBm] 37
PAE [%] 22
OIP3 [dBm] 48

21. PA Design  Hybrid Broadband PA (4)
 Example II: 5 W, 0.35 – 8 GHz PA
Transistor: GaN-HEMT, Cree (die)
BW [GHz]
0.35 – 8
Gain [dB]
8 ± 1.5
OP1dB [dBm] 37
PAE [%] 19
OIP3 [dBm] 51

22. PA Design  Hybrid Doherty PA (1)
DPA
Main PA  Class AB
Peaking PA  Class C
 Eff. Enhancement
Design phases
ADS Schematic
ADS Momentum
Realization and measurement
Specifications
UMTS downlink (2.1 GHz )
Pout > 50 W
PAE > 35% over 6-dB backoff

23. PA Design  Hybrid Doherty PA (2)
Small signal measurements
 ƒ=2.1 GHz
S11 [dB]
-8.5
S21 [dB]
9.6
S22 [dB]
-9.9

24. PA Design  Hybrid Doherty PA (3)
Large signal measurements
 ƒ=2.1 GHz
Gss [dB]
9.6
OP1dB [dBm]
47.2 (52 W)
OPSAT [dBm]
49.4 (87 W)
ηmax [%]
55.0
PAEmax [%]
45.0
η6-dB [%]
40.0
PAE6-dB [%]
34.0
Simulation - Solid lines
Measurement - Symbols

25. PA Design  Hybrid Switch Mode PA (1)
Switch mode classes
The output network creates non-overlapping waveforms
Dissipated power is low
 High efficiency is enabled
 Design of the device load network is decisive
Specifications
UMTS application
High efficiency is required
Supply voltage 50 V
Pout = 50 W A AB SM
IDS
IMAX IQ
VKnee
VDD
2VDD- VKnee
VDS

26. PA Design  Hybrid Switch Mode PA (2)
ADS Schematic design flow
Load-/Source-Pulling
Source  Targeted input power
 Bias point (Vg  class B/AB)
 Optimum impedances
Load  Harmonic load impedances as equation
Load Impedance for a class D-1 switch mode PA

27. PA Design  Hybrid Switch Mode PA (3)
Realization of class D-1 switch mode PA
 Eudyna GaN-HEMT
 3 dB hybrid coupler 90o
 Single stub OMN R Q1 Q2 S
Res.
OMN
Hybrid
90o
IMN
λ/4
50 Ω

28. PA Design  Hybrid Switch Mode PA (4)
Large signal results
 Pout = 47 dBm (50 W)
@ Pin = 33 dBm
 η = 62.7 %
 PAE = 60.3 %
meas
sim

29. PA Design  Monolithic 6 GHz PA (1)
Development of a fully integrated 6 GHz PA
Applications
 6 GHz Wireless LAN
 Vehicular environments (IEEE P802.11p)
Linear power amplifier
Class AB operation
Push-Pull topology
Low supply voltage
SiGe HBT technology

30. PA Design  Monolithic 6 GHz PA (2)
PA performance degrades with larger transistor arrays
 Power combining of several efficient PA stages with decreased transistor size
Integrated transformer is used as power combiner
Transformer design using ADS-Momentum
 PA design using EM/Co simulation in ADS

31. PA Design  Monolithic 6 GHz PA (3)
Realized GHz power amplifier
1.6 mm
1.3 mm
PIN [dBm]
POUT [dBm]
PAE [%]
VDD = 1.8 V
VDD = 1.2 V
f = 6 GHz
Freq.
[GHz]
VDD
[V]
OP1dB
[dBm]
OPsat
EtaMAX
[%]
PAEmax
SS Gain
[dB] 6
1.8 21 24
28.5 25 12

32. PA Design  Monolithic 24 / 60 GHz PA (1)
24 GHz ISM band
 Industrial, scientific and medical applications
Targets
 Gain > 13.5 dB
 OP1dB > 11 dBm
 PAE > 15 %

33. PA Design  Monolithic 24 / 60 GHz PA (2)
Vbias
RFin
Technology
 0.18 μm CMOS
Amplifier topology
 2 Stage cascode amplifier
 Simplified on-chip impedance matching using bias network to match the impedance.
Design procedure
 Circuit simulation on ADS
 Layout in cadence
 EM/Co simulation on ADS

34. PA Design  Monolithic 24 / 60 GHz PA (3)
Cadence Layout

35. PA Design  Monolithic 24 / 60 GHz PA (3)
Momentum simulation

36. PA Design  Monolithic 24 / 60 GHz PA (3)
Momentum simulation

37. PA Design  Monolithic 24 / 60 GHz PA (3)
ADS EM/Co Simulation

38. PA Design  Monolithic 24 / 60 GHz PA (3)
ADS EM/Co Simulation

39. PA Design  Monolithic 24 / 60 GHz PA (3)
Microphotograph of the PA die

40. PA Design  Monolithic 24 / 60 GHz PA (4)
Measures
 Good agreement between simulation and measurements
Freq [GHz]
26.5
VDD [V]
3.0
OP1dB [dBm]
13.5
OPsat [dBm]
17.5
P1dB [%]
12.3
Peak PAE [%]
22.5
Chip size [mm2]
0.73 x 1.15

41. PA Design  Monolithic 24 / 60 GHz PA (5)
60 GHz power amplifier
 High oxygen loss at 60 GHz
 Appropriate for indoor or short range wireless communication
60 GHz band

42. PA Design  Monolithic 24 / 60 GHz PA (6)
Requirements
High Power
High OP1dB
High PAE
High Gain
Selected Topology
Parallel stages
High Power Matching
Two Stage
Cascode } } IN
IMN
OMN
Biasing
Circuit
Matching

43. PA Design  Monolithic 24 / 60 GHz PA (7)
Matching network
Step 1: Load and source pull simulation
Matching for optimum OP1dB
Step 2: Selection of T.L.s, Inductors and Capacitors
ZOpt
Step 3: EM simulation of matching network
ZOpt
50 Ω

44. PA Design  Monolithic 24 / 60 GHz PA (8)
 60 GHz PA achievements
High Power
High Linearity
High PAE
High Gain
 Measurements
Freq.
[GHz]
Gain [dB]
OP1dB
[dBm]
OPsat
PAE
[%]
61.0
18.8
14.5
15.5
19.7

45. Summary and Conclusion
Excellent results using presented ADS PA design flow
Good agreement between EM/Co simulations and measurements
Applicable up to mm wave frequencies
Design procedure has been demonstrated for various PAs
 Hybrid Broadband Power Amplifier
 Hybrid Doherty Power Amplifier
 Hybrid Switch Mode Power Amplifier
 Monolithic 6 GHz Power Amplifier
 Monolithic 24 / 60 GHz Power Amplifier

46. Summary and Conclusion
Thanks