1. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning © KLMH Lienig 1 Modern Floorplanning Based on B*-Tree and Fast Simulated Annealing Presented by: Jie Zou University of Michigan Fall 2011

2. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning © KLMH Lienig 2 Modern Floorplanning Based on B*-Tree and Fast Simulated Annealing Introduction  Modern Floorplanning Based on B*-Tree and Fast Simulated Annealing Tung-Chieh Chen, Yao-Wen Chang, IEEE Transactions on computer-aided design of integrated circuits and systems, Vol. 25, No. 4, April 2006  VLSI floorplanning incurs more sophisticated constraints with the die outline, interconnect planning and block positions  Modern floorplanning is fixed-outline floorplanning  Two types of problems are studied  Fixed-outline floorplanning  Bus-driven floorplanning  Two types of methodology are used  B*-Tree to represent block positions  Fast SA as the floorplanning algorithm Fixed-Outline Bus-driven

3. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning © KLMH Lienig 3 ModernFloorplanning Based on B*-Tree and Fast Simulated Annealing B*-Tree Representation  Ordered binary tree  Root represents the block on the left-bottom corner  Left child of the node ni represents the lowest unvisited block that belongs to the set of blocks located on the right-hand side and adjacent to bi x j = x i + w i  Right child of the node ni represents the lowest block located above and with its x-coordinate equal to that of bi x j = x i b 0 b1b1 b 2 b 3 b4b4 b5b5 b 6 b 7 n0n0 n1n1 n3n3 n4n4 n2n2 n5n5 n7n7 n6n6

4. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning © KLMH Lienig 4 ModernFloorplanning Based on B*-Tree and Fast Simulated Annealing Fast SA  Motivation: To reduce the uphill moves in the beginning steps  Method: Resort to greedy algorithm to find the local optimal faster  Stages Decomposition 1.High-temperature random search stage 2.Pseudogreedy local-search stage 3.Hill-climbing search stage  Temperature updating function n: number of iterations ∆avg: average uphill cost ∆cost<1 since cost function is normalized

5. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning © KLMH Lienig 5 ModernFloorplanning Based on B*-Tree and Fast Simulated Annealing Fast SA  Boltzmann acceptance criterion: curr sol : current solution next sol : new solution after perturbation T: current temperature r: random number between[0,1) from normal distr.  Cost Function: A: current area W: current wirelength A norm : average area W norm : average wirelength

6. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning © KLMH Lienig 6 ModernFloorplanning Based on B*-Tree and Fast Simulated Annealing Fixed-Outline Floorplanning 1 4 2 3 0.79*1.26 = 0.9954 1 2 3 4 1.02*0.86=0.8772

7. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning © KLMH Lienig 7 ModernFloorplanning Based on B*-Tree and Fast Simulated Annealing Input: A set of blocks and a fixed outline Output: A floorplan within the outline Mark all non-rotatable blocks and set their orientations; Initialize a B*-tree with input blocks; // Start the adaptive Fast-SA process; T = T 0 // initialization do Perturb the B*Tree; Pack macro blocks; Evaluate the B*-tree cost; Decide if we should accept the new B*-tree; Modify the weights in the cost function; Update T; until converged or cooling down; return the best solution; Pseudocode

8. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning © KLMH Lienig 8 Modern Floorplanning Based on B*-Tree and Fast Simulated Annealing Input: A set of blocks and a fixed outline Output: A floorplan within the outline Mark all non-rotatable blocks and set their orientations; Initialize a B*-tree with input blocks; // Start the adaptive Fast-SA process; T = T 0 // initialization i = 0 curr_sol = init_sol curr_cost = COST(curr_sol) while (T > T min ) while (stopping criterion is not met) i = i + 1 (a i,b i ) = SELECT_PAIR(curr_sol)// perturb the B*tree trial_sol = TRY_MOVE(a i,b i )// try small local change trial_cost = COST(trial_sol)  cost = trial_cost – curr_cost if (  cost < 0)// if there is improvement, curr_cost = trial_cost// update the cost and curr_sol = MOVE(a i,b i )// execute the move else r = RANDOM(0,1)// random number [0,1] if (r < e –Δcost/T )// if it meets threshold, curr_cost = trial_cost// update the cost and curr_sol = MOVE(a i,b i )// execute the move T = α ∙ T Update T// 0 < α < 1, T reduction

9. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning © KLMH Lienig 9 ModernFloorplanning Based on B*-Tree and Fast Simulated Annealing Bus-Driven Floorplanning (BDF)  Problem statements  n rectangular macro blocks B = {b i |i = 1,..., n} & m buses U = {u i |i = 1,..., m}  each bus u i has a width t i and goes through a set of blocks B i, B i ⊆ B and |B i | = k i  no overlap between any two blocks or between any two horizontal (vertical) buses  bus u i goes through all of its k i blocks  the chip area and the bus area are minimized  Characteristics of buses  assigned on the top two metal layers  connect multiple blocks  either vertically or horizontally oriented  alignment constraint  blocks don’t need to be adjacent when connected by buses

10. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning © KLMH Lienig 10 ModernFloorplanning Based on B*-Tree and Fast Simulated Annealing Bus-Driven Floorplanning (BDF)  Bus constraints – alignment  Dummy blocks to ensure feasibility of horizontal buses

11. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning © KLMH Lienig 11 ModernFloorplanning Based on B*-Tree and Fast Simulated Annealing Bus-Driven Floorplanning (BDF)  In a B*-tree, the nodes in the right-skewed subtree can guarantee the feasibility of a vertical bus  Bus Overlapping

12. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning © KLMH Lienig 12 ModernFloorplanning Based on B*-Tree and Fast Simulated Annealing Bus-Driven Floorplanning (BDF)  Fixed I/O ports define fixed orientation of buses connected to the ports  Twisted buses

13. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning © KLMH Lienig 13 ModernFloorplanning Based on B*-Tree and Fast Simulated Annealing Bus-Driven Floorplanning (BDF)

14. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning © KLMH Lienig 14 ModernFloorplanning Based on B*-Tree and Fast Simulated Annealing Input: A set of blocks and a set of bus constraints Output: A floorplan satisfying bus constraints with minimized chip area and total bus area Initialize a B*-tree with input blocks; // Perform the Fast-SA process; T = T 0 // initialization do Perturb the B*Tree; Pack macro blocks without dummy blocks; if there exists a “twisted-bus structure” in the B*-tree; then restart the do-loop; Adjust the heights of the dummy blocks to fix horizontal bus constraints and fix bus- overlapping; Pack macro blocks with dummy blocks; Decide bus locations; Evaluate the floorplan cost; Decide if we should accept the new B*-tree; Update T; until converged or cooling down; return the best solution; Pseudocode

15. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning © KLMH Lienig 15 ModernFloorplanning Based on B*-Tree and Fast Simulated Annealing Application -- Parquet  Authors: Saurabh Adya, Hayward H. Chan, Igor Markov.  Latest version: PARQUET-4.5  Homepage: http://vlsicad.eecs.umich.edu/BK/parquet  Descriptions  free open-source software for fixed-outline floorplanning  based on Simulated Annealing  can also be applied to classical outline-free min-area block packing  internal floorplan representation alternates between sequence pairs and B*-Trees

16. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning © KLMH Lienig 16 ModernFloorplanning Based on B*-Tree and Fast Simulated Annealing Q&A Thank You !