1. © NUS 2005 TD5102 Embedded System in Silicon FPGA Architecture and EDA Dr. Ha Yajun (E1-08-17, elehy@nus.edu.sg)elehy@nus.edu.sg http://courses.nus.edu.sg/course/elehy/TD5102/

2. © NUS 2005 Yajun Ha / ECE, NUS 2 Embedded Systems An embedded system is nearly any computing system (other than a general-purpose computer) with the following characteristics Single-functioned Typically, is designed to perform predefined function Tightly constrained Tuned for low cost Single-to-fewer components based Performs functions fast enough Consumes minimum power Reactive and real-time Must continually monitor the desired environment and react to changes Hardware and software co-existence

3. © NUS 2005 Yajun Ha / ECE, NUS 3 Embedded Systems Examples: Communication devices Wired and wireless routers and switches Automotive applications Braking systems, traction control, airbag release systems, and cruise-control applications Aerospace applications Flight-control systems, engine controllers, auto-pilots and passenger in-flight entertainment systems Defense systems Radar systems, fighter aircraft flight-control systems, radio systems, and missile guidance systems

4. © NUS 2005 Yajun Ha / ECE, NUS 4 Simplified and General Embedded System Design Methodology SW/HW Interface Algorithm Functional Modeling Problem Partitioning Software Func. Model SW/HW Interface Hardware Func. Model Architectural synthesis Software Development Structural RTL HDL Application Source Code Processors Application Specific Hardware(ASIC/FPGA) Platforms Algorithms

5. © NUS 2005 Yajun Ha / ECE, NUS 5 Three Kinds of Embedded System Implementation Platform Choices Rf D$ I$ Sw ID +|-|*|>| + - * > Configuration Sw Processor Reconfigurable FPGA Hardwired ASIC Programmable Sequential Instruction flow (cycle) Transfer bottleneck Configurable Parallel wired algorithm “Program” flow (occasionally) Distributed data + - * > No wiring No configuration Overhead + - * > Power: 100 10 1

6. © NUS 2005 Yajun Ha / ECE, NUS 6 Why Use Reconfigurable Hardware? Processor Processor- ASIC Processor- FPGA Performance LowHighMedium Flexibility HighLowHigh Power HighLowMedium Combine flexibility with performance. Shorter time-to-market and longer time-in-market. #FPGA gates/USD: 2004 1 M/10$. FPGA capacity: now 2004 50Mgates => FPGAs get used as functional part of a design ( prototyping) Why FPGAs ?

7. © NUS 2005 Yajun Ha / ECE, NUS 7 Embedded Software Tools CPU Logic Design Tools I/O FPGA Memory Logic Design Tools FPGA + Memory + IP + High Speed IO (4K & Virtex  ) Embedded Software Tools CPU Integration of Functions Time Logic Design Tools Embedded Software Tools Logic + Memory + IP + Processors + RocketIO (Virtex-II Pro  ) Programmable Systems usher in a new era of system design integration possibilities Programmable Systems usher in a new era of system design integration possibilities Integration in System Design

8. © NUS 2005 Yajun Ha / ECE, NUS 8 FPGA Based Reconfigurable Platform  Reconfigurable Platforms Architectures EDA for Reconfigurable Architectures Applications of Reconfigurable Platforms Lab Sessions on FPGA Board

9. © NUS 2005 Yajun Ha / ECE, NUS 9 Simplified FPGA Architecture Functional Block I/O Block Routing Network All the three components can be re-programmed with configurations to implement application-specific digital circuits. For example, each functional block can be programmed to implement a small amount of digital logic of a design; the routing network can be programmed to implement the design specific interconnection pattern; I/O blocks can be programmed to implement the input and output ports according to design requirements.

10. © NUS 2005 Yajun Ha / ECE, NUS 10 FPGA Reconfiguration All the programming information for the three programmable RA components is stored in a configuration file. The configuration file for a RA is often called a bitstream compared to a binary executable for a processor. Once a bitstream for a digital logic design is downloaded to a RA, the RA is programmed to implement the design. By providing different bitstreams, a single RA can be re- programmed to implement different designs at different times. Bitstream File 1 Bitstream File 2 Time 1 Time 2

11. © NUS 2005 Yajun Ha / ECE, NUS 11 FPGA Functional Block LE Local Inter- connect ….. Functional Block Inputs Functional Block Outputs Functional Block Internals Our target RAs use the Look-Up Table (LUT) type of functional block. Such a functional block is normally made of one or several logic elements (LE). They differentiate from each other mainly in terms of the input size of a LE and the number of LEs in a functional block. State-of- the-art RAs normally use 4-input LEs.

12. © NUS 2005 Yajun Ha / ECE, NUS 12 FPGA Logic Element LE Internals The LE consists of a 16 SRAM cell Look-Up Table (LUT), and a flip flop (FF). The 16 SRAM cells LUT stores the truth table of any 4-input logic function, thus it can implement any 4-input logic function. The FF implements the storage element in a sequential circuit.

13. © NUS 2005 Yajun Ha / ECE, NUS 13 LUT Content F = A*B+C*D ABCD F 0000 0 0001 0 0010 0 0011 1 0100 0 0101 0 0110 0 0111 1 1000 0 1001 0 1010 0 1011 1 1100 1 1101 1 1110 1 1111 1 ABCDABCD F The 16 SRAM cell LUT stores the output column of the truth table of the F function. The 4 inputs A, B, C and D will determine which bit the F value is for the current values of A, B, C and D.

14. © NUS 2005 Yajun Ha / ECE, NUS 14 Additional Computational Resources Memory blocks Microprocessor blocks Besides the LEs present in previous slide, some functional blocks in different target RAs have architecture specific features to improve the performance when implementing arithmetic functions. These architecture specific features include carry logic, embedded memory blocks, multiplier and other hard cores. Hard cores generally implement functions efficiently compared to FPGA functional blocks.

15. © NUS 2005 Yajun Ha / ECE, NUS 15 FPGA Routing Architecture A logic block input or output pin can connect to some or all of the wiring segments in the channel adjacent to it via a connection block of programmable switches. At every intersection of a horizontal channel and a vertical channel, there is a switch block. It is a set of programmable switches that allow some of the wire segments incident to the switch block to be connected to others. By turning on the appropriate switches, short wire segments can be connected together to form longer connections.

16. © NUS 2005 Yajun Ha / ECE, NUS 16 FPGA Routing Wires Some target RAs contain routing architectures that include different lengths of wires. The length of a wire is the number of functional blocks it spans. Left figures show wires of length 1, 2 and 4.

17. © NUS 2005 Yajun Ha / ECE, NUS 17 XC4000 Routing Architecture Example

18. © NUS 2005 Yajun Ha / ECE, NUS 18 Commercial FPGA Architecture Comparison

19. © NUS 2005 Yajun Ha / ECE, NUS 19 PowerPC 405 Core Dedicated Hard IP Flexible Soft IP RocketIO PowerPC-based Embedded Design Full system customization to meet performance, functionality, and cost goals DCR Bus UART GPIO On-Chip Peripheral Hi-Speed Peripheral GB E-Net e.g. Memory Controller Arbiter On-Chip Peripheral Bus OPB Arbiter Processor Local Bus InstructionData PLB DSOCM BRAM ISOCM BRAM Off-Chip Memory ZBT SRAM DDR SDRAM SDRAM Bus Bridge IBM CoreConnect™ on-chip bus standard PLB, OPB, and DCR

20. © NUS 2005 Yajun Ha / ECE, NUS 20 MicroBlaze-based Embedded Design Flexible Soft IP MicroBlaze  32-Bit RISC Core UART 10/100 E-Net On-Chip Peripheral Off-Chip Memory FLASH/SRAM LocalLink™ FIFO Channels 0,1…….32 Custom Functions Custom Functions BRAM Local Memory Bus D-Cache BRAM I-Cache BRAM Configurable Sizes Possible in Virtex-II Pro Arbiter OPB On-Chip Peripheral Bus

21. © NUS 2005 Yajun Ha / ECE, NUS 21 FPGA Based Reconfigurable Platform  Reconfigurable Platforms Architectures  EDA for Reconfigurable Architectures Applications of Reconfigurable Platforms Lab Sessions on FPGA Board

22. © NUS 2005 Yajun Ha / ECE, NUS 22 FPGA Design Flow

23. © NUS 2005 Yajun Ha / ECE, NUS 23 Time Profile for Design Flow Steps Logic Optimization and routing steps normally consume the major part of the design flow time.

24. © NUS 2005 Yajun Ha / ECE, NUS 24 FPGA Technology Mapping Technology step restructures the primitive logic gates, generated from the logic optimization step, into sets of 4-input functional blocks.

25. © NUS 2005 Yajun Ha / ECE, NUS 25 FPGA Placement and Routing The placement step finds physical locations for functional blocks, while the routing step finds physical routes for logic connections.

26. © NUS 2005 Yajun Ha / ECE, NUS Embedded Design in an FPGA Embedded design in an FPGA consists of the following: FPGA hardware design C drivers for hardware Software design RTOS versus Main + ISR

27. © NUS 2005 Yajun Ha / ECE, NUS 27 Embedded Development Tool Flow Overview Compiler/Linker (Simulator) C Code Debugger Standard Embedded SW Development Flow CPU code in on-chip memory ? CPU code in off-chip memory Download to Board & FPGA Object Code Standard FPGA HW Development Flow Synthesizer Place & Route Simulator VHDL/Verilog ? Download to FPGA

28. © NUS 2005 Yajun Ha / ECE, NUS Embedded Development Kit The Embedded Development Kit (EDK) consists of the following: Xilinx Platform Studio – XPS Base System Builder – BSB Create and Import Peripheral Wizard Hardware generation tool – PlatGen Library generation tool – LibGen Simulation generation tool – SimGen GNU software development tools System verification tool – XMD Virtual Platform generation tool - VPgen Software Development Kit (Eclipse) Processor IP Drivers for IP Documentation Use the GUI or the shell command tool to run EDK Detailed data sheet of Xilinx FPGA devices and user manuals of ISE and EDK tools are available online at http://www.xilinx.com/support/library.htm

29. © NUS 2005 Yajun Ha / ECE, NUS 29 FPGA Based Reconfigurable Platform  Reconfigurable Platforms Architectures  EDA for Reconfigurable Architectures  Applications of Reconfigurable Platforms Lab Sessions on FPGA Board

30. © NUS 2005 Yajun Ha / ECE, NUS 30 Why Networked Hardware? But one day Cindy cried and told me that our talk had been disclosed. I laughed and said “Baby, never mind, I will change the encryption instantly through the network!!!” Cindy Crawford asked me to encrypt our mobile phone talk!!! It is not an easy job!!! So I resort to hardware. --- Quoted from Cindy’s Boy Friend!!!

31. © NUS 2005 Yajun Ha / ECE, NUS 31 Future Networked Applications Need Client Platforms with Flexible Hardware Acceleration Future networked applications can require high computing power up to 1000 Giga Ops [Nakatsuka, ISSCC’99], thus hardware acceleration is generally needed, and networked applications will contain both software and hardware components. Different networked applications may use different industry standards to support new services, and require the client platforms to be flexible. Networked applications usually work with a server- client model, and require the client platforms to be connected to the network.

32. © NUS 2005 Yajun Ha / ECE, NUS 32 Target Client Platform: Networked Reconfigurable Platform Dowloading SW Part HW Part Application Description ISP 1 ISP 2 ISP N Distr. memory arch. ASIC Reconfigurable Hardware static interconnect network Both ISP and reconfigurable HW can be programmed to adapt changing standards. Reconfigurable HW can provide a better than ISP energy efficiency of high processing power vs. power consumption. Configurations for both ISP and reconfigurable HW can be network downloaded. flexible! High computing power! networked!

33. © NUS 2005 Yajun Ha / ECE, NUS 33 Commercial FPGA Platform Dowloading SW Part HW Part Application Description ISP 1 ISP 2 ISP N Distr. memory arch. ASIC Reconfigurable Hardware static interconnect network Both ISP and reconfigurable HW can be programmed to adapt changing standards. Reconfigurable HW can provide a better than ISP energy efficiency of high processing power vs. power consumption. Configurations for both ISP and reconfigurable HW can be network downloaded. flexible! High computing power! networked! ReConfig. logic Up to 16 serial transceivers PowerPCs Courtesy of Xilinx (Virtex II Pro)

34. © NUS 2005 Yajun Ha / ECE, NUS 34 Networked SW/HW Reconfiguration of Networked Information Appliance Web Page User Download s App User Selects App Advertise App on Web Page Dowloading Java File HW File Description ISP 1 ISP 2 ISP N Distr. memory arch. ASIC Re-configurable Hardware static interconnect network

35. © NUS 2005 Yajun Ha / ECE, NUS 35 Web MPEG Video Player Client Web Page Server Side Client Side Java MPEG Player + IDCT bitstream CPU + FPGA

36. © NUS 2005 Yajun Ha / ECE, NUS 36 Networked Reconfiguration is Better Service Provider Service Client Service Request network Service I Reconfig Info Service I Data Streams Service II Data Streams …... Service II Reconfig Info

37. © NUS 2005 Yajun Ha / ECE, NUS 37 FPGA Based Reconfigurable Platform  Reconfigurable Platforms Architectures  EDA for Reconfigurable Architectures  Applications of Reconfigurable Platforms  Lab Sessions on FPGA Board  Lab Session 1: Reconfigurable fabric based hardware design  Lab Session 2: Processor+Reconfig Fabric based system design

38. © NUS 2005 Yajun Ha / ECE, NUS 38 MEMEC Virtex-4 LC FPGA Board More FPGA board related documentations have been put online at http://courses.nus.edu.sg/course/elehy/EE4218/projects.htm FPGA Push Buttons LEDs DIP Switches Serial Port

39. © NUS 2005 Yajun Ha / ECE, NUS 39 FPGA Board Demo When PUSH2 (SW5) is not held down, the 7-segment display (DD1) does a binary-to-hex conversion of the binary number represented by the 4-bit DIP switch (SW3). When PUSH2 (SW5) is held down, the 7-segment display (DD1) counts from 0-9. LED1, LED2, LED3, and LED4 count in binary from 0-9 (matching what is on DD1 when PUSH2 is pressed). Pushing PUSH1 resets the counter. SW5 PUSH2 7-segment Display

40. © NUS 2005 Yajun Ha / ECE, NUS 40 FPGA Lab 1 & 2 Please print relevant docs by yourself and bring to labs! Watch the FPGA board demo closely Lab 1: Try to re-implement the demo with Xilinx ISE on your FPGA board and do the assignment Design files for the demo will be installed on your PC. You need to use Xilinx ISE tool to generate and download the bitstream. Get familiar with Xilinx ISE environment and link the various FPGA design flow steps to the tool. Browse and understand the design files for the demo. Lab 2: Follow the Xilinx EDK tutorial that can be found in the TD5102 course web site under project page. Lab session in Signal Processing and VLSI Lab (E4-08-34) 2:00-5:00pm on 13 & 14 Dec!

41. © NUS 2005 Yajun Ha / ECE, NUS 41 Summary FPGA architectures have been introduced. EDA tools for FPGAs have been introduced. Applications of FPGA for networked platforms have been introduced. Lab introduction.