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Embedded Design with The Xilinx Embedded Developer Kit Xilinx Training.

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Presentation on theme: "Embedded Design with The Xilinx Embedded Developer Kit Xilinx Training."— Presentation transcript:

1 Embedded Design with The Xilinx Embedded Developer Kit Xilinx Training

2 Welcome If you are new to Embedded design with Xilinx FPGAs, this module will help you start planning your design Understanding the difference between Xilinx’s FPGA architectures is essential if you are going to select an appropriate FPGA device family The Embedded Developers Kit software (EDK) is designed to make building a custom embedded design easy

3 Objectives After completing this module, you will be able to: Choose between a PPC 440 and a MicroBlaze processor system Explain the primary tool functionality included with the Embedded Developers Kit (EDK) Explain the benefits of building an embedded design with an FPGA

4 Hardware Introduction Overview of EDK Embedded Development Design Flow Summary Lessons

5 Xilinx Embedded Processor Innovation PerformanceIntegrationFlexibilityFeatures 32-bit RISC Processor Soft Core 32-bit RISC Processor Soft Core PLB46 Embedded Development Kit IP PowerPC 440 Embedded Block with Integrated Interconnect PowerPC 440 Embedded Block with Integrated Interconnect PowerPC® 405 Hard Core Hard Core in Virtex®-II PRO FPGA PowerPC® 405 Hard Core Hard Core in Virtex®-II PRO FPGA 2000 2002 2004 2008 2006 PowerPC 405 Hard Core Hard Core in Virtex-4 FX FPGA PowerPC 405 Hard Core Hard Core in Virtex-4 FX FPGA

6 Supported FPGAs FPGA families –Spartan-3/3A/3AN/3A DSP/3E FPGA (MicroBlaze processor) –Spartan-6 (MicroBlaze Processor) –Virtex-4 FX (MicroBlaze and PowerPC 405 processors) and LX/SX FPGA (MicroBlaze processor) –Virtex-5 FXT (MicroBlaze and PowerPC 440 processor) LX/LXT FPGA (MicroBlaze) –Virtex-6 (MicroBlaze processor)

7 Embedded Design in an FPGA Embedded design in an FPGA consists of the following –FPGA hardware design Processor system  MicroBlaze processor (soft core)  PowerPC processor (PPC440 hard core)  PLB bus components Other FPGA hardware –Software platform for processor system Standalone  C language support  Processor services  C drivers for hardware Third-party operating systems (optional) –User software application

8 PowerPC Processor-Based Embedded Design Full system customization to meet performance, functionality, and cost goals UART GPIO Bus Master Hi-Speed Peripheral GB E-Net e.g. Memory Controller PLB v46 Off-Chip Memory ZBT SSRAMDDR SDRAM SDRAM PLB v46 DDR SPLBMPLB TEMAC PowerPC 440 Core Dedicated Hard IP MCI DMA PPC DDR2 Memory Controller

9 MicroBlaze Processor-Based Embedded Design Flexible Soft IP MicroBlaze  32-Bit RISC Core UART Memory Controller Off-Chip Memory FLASH/SRAM Fast Simplex Link 0,1….7 Custom Functions Custom Functions BRAM Local Memory Bus D-Cache BRAM I-Cache BRAM Configurable Sizes Possible in Virtex™-5 FXT PLB v46 CacheLink SRAM PLB v46 MPLB Dedicated Hard IP PowerPC 440 Core Dedicated Hard IP GB E-Net Hi-Speed Peripheral SPLB

10 IP Peripherals All are included FREE! Bus infrastructure and bridge cores Memory and memory controller cores Debug Peripherals Arithmetic Timers Inter-processor communication External peripheral controller DMA controller PCI User core template …and Other cores

11 Hardware Introduction Overview of EDK Embedded Development Design Flow Summary Lessons

12 Embedded Development Kit What is the Embedded Development Kit (EDK)? –The Embedded Development Kit is the Xilinx software suite for designing Complete embedded programmable systems Processor sub-system component of larger design –The kit includes all the tools, documentation, and IP that you require for designing systems with embedded IBM PowerPC 440 hard processor cores and/or Xilinx MicroBlaze soft processor cores –SDK Eclipse-based software design environment –It enables the integration of both hardware and software components of an embedded system

13 XPS Functions  Platform management –System create wizard (BSB) –Netlist Generation (PlatGen) –Custom Peripheral creation wizard –Hardware Debugging (ChipScope) –Hardware Simulation (SimGen) XPS Software Design - SDK Hardware Design HW/SW Debug HW/SW Simulation  Software application management –Software library generation (LibGen) –Software Profiling –Xilinx Microprocessor Debugger (XMD) and Software Debugging –Xilinx MicroKernel (XMK)

14 Xilinx Platform Studio (XPS) See the Notes section for a detailed description System Assembly View Connectivity Panel Project Information Area Console

15 Hardware Introduction Overview of EDK Embedded Development Design Flow Summary Lessons

16 Embedded Development Design Flow Create a new EDK project Use the Base System Builder (BSB) to construct your basic embedded design Run PlatGen to make your HDL instantiation files and netlist for each component in your embedded design Implement the embedded design with the ISE software Create and compile your software with SD Merge your compiled software with the FPGA bitstream using the Data2MEM utility Download your FPGA’s completed bitstream using iMPACT

17 Launching a New XPS Project It is recommended that XPS processor projects be launched from Project Navigator in the ISE software –Easy to integrate a processor sub- system with other FPGA logic –Access to more Xilinx point tools –Easy software integration The processor sub-system can be placed anywhere in the design hierarchy More on this in later modules

18 Starting out with a Processor Design Many vendors support evaluation and demo boards with Xilinx FPGAs –Xilinx –Avnet –Digilent Base System Builder (BSB) is a wizard to facilitate a fast processor-based system design by high abstraction, level-specification entry Virtex®-5 FPGA ML507 Spartan®-3E FPGA 1600E

19 Project Creation Using the Base System Builder Select a target board Select a processor Configure the processor Select and configure I/O interfaces Add internal peripherals Generate system software and a linker script Generate the design –Generated files include the following system.mhs system.xmp data/system.ucf pcore directory (empty)

20 Generating the Processor Hardware Netlist Select Hardware  Generate Netlist Platform Generator: PlatGen –Input file  MHS and MPD The MHS file defines the configuration of the embedded processor system, including the bus architecture, peripherals and processor(s), interrupt request priorities, and address space The MPD file defines the configurable parameters with their default values and available ports for a peripheral –Output files  system netlist, peripheral netlists, and BMM file –Creates the synthesis, HDL, and implementation directories –Generates the HDL wrapper files for the peripherals –Generates the top-level system HDL file –Extracts the peripheral netlists from the EDK install directory –Generates the BMM file –Calls XST to synthesize the top-level wrapper file

21 Detailed EDK Design Flow Processor IP MPD Files system.ucf Create FPGA Programming (system.bit) MHS File system.mhs PlatGen FPGA Implementation (ISE/Xflow) Hardware Data2MEM download.bit Compile Link Object Files Executable Libraries Source Code (C code) LibGen EDIF IP Netlists Source Code (VHDL/Verilog) Synthesis Standard Embedded Software Flow Standard Embedded Hardware Flow

22 Software Flow Software development is performed with the Xilinx Software Development Kit (SDK) A hardware image XML file must first be generated to define the hardware platform for which the software application will be developed The SDK software tools will then attach the software project to the hardware SDK can be launched now or later, Export Only

23 SDK Software Development SDK software development –Create software platform System software, board support package LibGen program –Create software application –Create Linker Script –Build project  compile, assemble, link –Output file  executable.elf

24 Merging Hardware and Software Flows Data2MEM download.bit MicroBlaze/ PPC UART Arbiter GPIO Hardware Flow Software Flow  FPGA Partial Reconfiguration enables the reprogramming of the Block RAM contents without reprogramming the entire FPGA –Saves download time –Saves re-implementation time –Enables software debugging  Use of off-chip RAM encouraged for large pieces of software (typical)

25 Configuring the FPGA Download the bitstream –Input file  download.bit –This downloads the download.bit file onto the target board by using the Xilinx iMPACT tool in batch mode Accessible from all tools –XPS –SDK –Project Navigator Requires that the download cable is connected SDK ISE Tool XPS

26 Virtex-5 FPGA ML507 Lab Board RS-232 cable – transmits serial information from your PC to your embedded system (the other end is attached to the PC). A null modem is needed. Xilinx USB platform cable – configures the FPGA (the other end is attached to the USB port of the PC) High-performance ribbon cable

27 Demo Boards  Lab instructions are provided for both the PowerPC 440 and MicroBlaze processors Spartan-3E FPGA XC3S1600E MicroBlaze Development Board Spartan-6 FPGA LXT SP605 MicroBlaze Development Board Virtex-5 FPGA FXT ML507 PowerPC Evaluation Platform

28 Hardware Introduction Overview of EDK Embedded Development Design Flow Summary Lessons

29 Summary The Embedded Development Kit (EDK) includes all the tools, documentation, and IP necessary for building embedded systems The Software Development Kit (SDK) is a comprehensive software development environment for simple software and firmware for complex applications The Base System Builder (BSB) makes it easy to build a full hardware design targeting an available demo board Merging software into an FPGA hardware bitstream is completed with the Data2MEM utility (Update Bitstream) Hardware netlists for an embedded design are implemented with the ISE tools

30 Where Can I Learn More? Xilinx Embedded Processing page –www.xilinx.com/embedded –Learn more about Embedded Design Kits for all Xilinx product families Xilinx online documents –support.xilinx.com Getting Started with the Embedded Development Kit Processor IP Reference Guide  Right-click any peripheral from the IP Catalog to learn more about it Embedded Systems Tools Guide Xilinx Drivers Processor reference guides  PowerPC 405/440 Processor Block Reference Guide  MicroBlaze Processor Reference Guide For all docs, select Help  EDK Online Documentation from the EDK tools

31 Where Can I Learn More? Xilinx Training Courses –www.xilinx.com/training Embedded Systems Development course  Rapidly architect an embedded system  Introduction to most of the EDK tools Embedded Systems Software Development course  Rapidly architect an embedded software system  Introduction to the SDK (Software Development Kit) Advanced Embedded Systems Development course  Take advantage of advanced features of the PPC440  Apply advanced debugging techniques including ChipScope  Design a Flash memory-based system and boot load from off-chip Flash memory Customers spend 50% of their time in lab

32 What’s Next? Related Video Courses –Embedded Design with the MicorBlaze Soft Processor Core –Embedded Design with the PPC 440

33 Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes. Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents, copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design. Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design. THE DESIGN IS PROVIDED “AS IS" WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE, WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DESIGN, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOST DATA AND LOST PROFITS, ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN, EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH YOUR USE OF THE DESIGN, WHETHER IN CONTRACT OR TORT OR OTHERWISE, WILL IN NO EVENT EXCEED THE AMOUNT OF FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN. YOU ACKNOWLEDGE THAT THE FEES, IF ANY, REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY. The Design is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring fail-safe controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or weapons systems (“High-Risk Applications”). Xilinx specifically disclaims any express or implied warranties of fitness for such High-Risk Applications. You represent that use of the Design in such High-Risk Applications is fully at your risk. © 2012 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners. Trademark Information


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