1. Combining High Level Synthesis and Floorplan Together EDA Lab, Tsinghua University Jinian Bian

2. Outlines Background Combining High Level Synthesis and Floorplan together The evolution of Combing HLS and Floorplan The Basic Structure of Combining HLS and Floorplan Conclusion and our future work

3. Background The progress of manufactory technique for silicon chips has been slowed down under traditional design methodology High performance / Low cost / Low power should be achieved by a more refined design, which means we need more powerful EDA tools

4. Background The traditional EDA methodology has been challenged The interconnect takes up most of resources: including area resource, delay resource, and power resource, etc. The traditional design flow may cause a long design time, low design quality, even design failure under nanometer design environment High performance / Low cost / Low power should be achieved by a more refined design, which means we need more powerful EDA tools

5. Traditional Design Flow High Level Synthesis Floorplan HLS Optimize OK ? FP Optimize OK ? Chip Optimize OK? N Y N Y N

6. Problems High Level Synthesis and Floorplan are based on different Optimization Model No Interconnect Information in High Level Synthesis No Behavior Information in Floorplan May cause a long design time, low design quality, even design failure

7. Forgoing Optimized Flow High Level Synthesis Meet Constraints ? Fast Floorplan HLS & Fast FP Optimized OK ? Final Floorplan Chip Optimized OK ? N Y Y N Y Y N Y

8. Forgoing optimized Flow High level synthesis using floorplan to get some physical information; Re-synthesis after floorplanning to optimize the design. But, Long loop time ； The estimation of Interconnect Information may far from final Chip ； Floorplan is passive.

9. Optimized Design Flow Interconnect Information can be got through a fast floorplan tool The estimation of Interconnect Information may far from final Chip

10. Proposed New Design Flow High Level SynthesisFloorplan Q/A The Chip Controller

11. Proposed Design Flow High Level Synthesis and Floorplan can communicate with each other The functionality of High Level Synthesis and Floorplan are both enhanced The result of allocation and scheduling can be restructured by Floorplan The Information of Interconnect can be retrieved easily The optimization of HLS and FP are based on a same estimation model Evolutional synthesis and floorplanning, to guarantee quicker astringency

13. Target Design Flow The main loop from High Level Synthesis and Floorplan can be avoid The optimizations of High Level Synthesis and Floorplan are consistent Can achieve a shorter running time of tools and a better quality of circuits

14. To Achieve the “ Target Design Flow ” 1. High Level Synthesis Oriented Physical Information Estimation 2. Floorplan Aware High Level Synthesis 3. Behavior Aware Floorplan 4. High Level Synthesis and Floorplan Oriented Parameterized Functional Unit Library

15. 1. High Level Synthesis Oriented Physical Information Estimation HLS oriented high level physical information model and estimation technology Physical Information Estimation oriented fast floorplan and placement

16. 1.1 HLS oriented physical information model and estimation technology of a module To create HLS oriented physical information model ， through studying the existing information of physical design and IP core To study the relationship of logic struction vs. physical information (interconnect, power, conjestive, etc.) before phsical design

17. 1.2 quick floorplanning technique to estimate physical information To get physical information with different accurate Techniques: Partitioning and clustering Quick floorplanning algorithm Placement information in a module

18. 2. Floorplan Aware High Level Synthesis Floorplan aware High Level Synthesis Pre-partition before floorplan Interconnect aware HLS Analysis and Information retrieval of the result of Floorplan Constraints generation for Floorplan Incremental High Level Synthesis after Floorplan

19. Floorplan Aware High Level Synthesis Constraints from HLS to floorplan boundary constraints, adjacent constraints, separation constraints, delay constraints of each net, alternative modules for each functional unit, area constraints, etc. Constraints from floorplan to HLS delay constraints for each functional unit, area constraints for each functional unit, etc.

20. High Level Physical Information Estimation Scheduling and Allocation Floorplan Floorplan Constraints Generation FeedBack: HLS Constraints Generation Delay Constraint In HLS Adjacent Constraint In Floorplan Allocation Constraint In HLS

21. 2.1. HLS techniques combined with floorplanning HLS algorithm considering physical info. of every module and the interconnect information between modules Get information from a module library with functionality and performance parameters and justify the design result Technology mapping and functional unit assignment

22. 2.2 floorplanning constraint generation after HLS To transfer the information, requests and constraints of HLS to floorplanning E.g. group information, adjacent relationship, critical paths, etc.

23. 2.3 Re-synthesis after floorplanning Adjust functional unit assignment and binding without florplan result to enhance the performance. Adjust schedule result to change the timing constraint To enhance the layout result.

24. 3. Behavior Aware Floorplan Behavior aware Floorplan Partition and Clustor based on behavior information Floorplan under uncertain data Floorplan can change the result of allocation from HLS Incremental Floorplan after High Level Resynthesis

25. 3.1. Constraints and behavior driven floorplanning To satisfy the circuit functionality and timing constaints Behavior constraints are as a guidance for floorplanning

26. 3.2. floorplanning technique with incomplete information including ： Undetermined module shapes or areas Undetermined pins ， Undetermined module numbers Possible solutions Soft-module floorplanning techniques Shape-alterable polygons Unit and module mixed Etc.

27. 3.3. Incremental floorplanning after synthesis To keep the basic structure and to keep the parameter unchanged.

28. 4. HLS and Floorplan Oriented Parameterized FU Library Functional Unit Interface for both High Level Synthesis and Floorplan Provide prototype and instance of each functional unit Fast Estimation of physical information for un-stored functional unit

29. Conclusion and future work The main frame of Combining High Level Synthesis and Floorplan The structure of the parameterized functional unit library

30. Conclusion and future work Floorplan aware High Level Synthesis Floorplan under uncertain conditions Constraints and feedback generation and transfer between High Level Synthesis and Floorplan

31. Thank You!