1. EE 587 SoC Design & Test Partha Pande School of EECS Washington State University pande@eecs.wsu.edu

2. 2 I DDQ Current Testing

3. Basic Principle of I DDQ Testing n Measure I DDQ current through V ss bus

4. Basic Principles n IDDQ testing refers to the integrated circuit (IC) testing method based upon measurement of steady state power-supply current. n Iddq stands for quiescent Idd, or quiescent power- supply current. n in case of a defect such as gate-oxide short or short between two metal lines, a conduction path from power-supply (Vdd) to ground (Gnd) is formed and subsequently the circuit dissipates significantly high current. n This faulty current is a few orders of magnitude higher than the fault-free leakage current. n Iddq testing provides physical defect oriented testing

5. Physical Defects n Wafer defects are found in clusters. These clusters are randomly distributed over the whole wafer. Every part of the wafer has an equal probability of having a defect cluster. n Any part of a diffusion, Polysilicon, or metal line may have an open fault. Any contact between any two layers may be open. n Bridging may occur between any two electrical nodes, whether they belong to one layer or different layers n Only a small percentage of bridging and open faults can be modeled at the stuck-at level. The actual distribution varies and largely depends on the technology and fabrication process.

6. Bridging

7. in the presence of bridging, a conduction path is formed from Vdd to Gnd. Subsequently, the circuit dissipates a large current through this path, and thus, simple monitoring of the supply current can detect bridging.

8. Floating Gate Defects n Small break in logic gate inputs (100 – 200 Angstroms) lets wires couple by electron tunneling  Delay fault and I DDQ fault n Large open results in stuck-at fault – not detectable by I DDQ test  If V tn < V fn < V DD - | V tp | then detectable by I DDQ test

9. Capacitive Coupling of Floating Gates n C pb – capacitance from poly to bulk n C mp – overlapped metal wire to poly n Floating gate voltage depends on capacitances and node voltages n If nFET and pFET get enough gate voltage to turn them on, then I DDQ test detects this defect

10. NAND Open Circuit Defect – Floating gate

11. Open  Not very effective for open defects  The vector AB=01 sensitizes the open  In the presence of the open output of the gate is in high impedance  The vector before the sensitization vectors defines the logic values at the output

12. Iddq Testing in SoCs n SoCs contain huge number of transistors n Summation of leakage current of all transistors becomes too large to distinguish between faulty and fault-free chips n Most of the SoCs contain multiple power supplies n Iddq testing is done on one power supply at a time

13. Iddq Testing in DSM n The theoretical basis of Iddq testing is based upon estimation of defect-free current in the circuit and then setting a limit (popularly, called as Iddq threshold) above which a circuit is considered defective.

14. Iddq Testing in DSM n When the density functions of defect-free and defective current are separate from each other, the clear distinction between the good and the defective IC can be made. n However, with technology shrink (increased sub- threshold leakage) and increasing number of gates in an IC, the mean value of the distribution of defect-free current increases and approaches the Iddq threshold limit (set from earlier technology). n Just changing the threshold limit to a higher number does not resolve the issue because with high leakage in the circuit, change in defect-free and defective current is very small

15. Iddq Testing in DSM Two mechanisms have been proposed to reduce I off : reduced temperature and substrate bias.

16. Design-for-Iddq-Testing n Avoid any possible static high current state in the circuit; if a high current state is unavoidable, then re-design so that it can be isolated during Iddq testing. n All static current dissipating logic should be switched off, this includes memory sense-amps, dynamic logic, asynchronous logic, pull-up/pull- down resistors, special I/O buffers and analog circuitry.

17. Design-for-Iddq-Testing Global control signal to switch off static current dissipating logic

18. Iddq Testing in SoC n The global power-down control signal based design methodologies are also very important for system- on-a-chip (SoC) designs using embedded cores. n In SoCs we need one power supply control signal per core n One pin per core is needed n Extra overhead

19. JTAG & Iddq

20. Iddq Testing in SoC n Some type of partitioning method is needed for Iddq testing in embedded core-based system chips n Power_Down control signals are used to selectively switch off portions of the SoC

21. Iddq Testing in SoC

22. n Four instructions n Power_Down_A, Power_Down_B, Power_Down_C, Power_Down_Main n When any one of these instructions are loaded into the boundary scan instruction register, one Power_Down signal is kept at 1 while all other Power_Down signals are set to 0 n The Power_Down control signals at 0 cuts off the power supply of the respective blocks n Power_Down_Main n It sets all Power_Down signals to 0 n Testing of the glue logic

23. Iddq Testing in SoC n The previous method can be applied to IEEE P1500 standard n We need to modify the Wrapper Instruction Register

24. Difference in Histograms n A – test escapes, B – yield loss

25. Delta I DDQ Testing n Use derivative of I DDQ at test vector i as current signature ΔI DDQ (i) = I DDQ (i) – I DDQ (i – 1) n Leads to a narrower histogram n Eliminates variation between chips and between wafers Select decision threshold Δ def to minimize probability of false test decisions

26. Iddq Measurements n Generally it is performed at a slow speed n The necessary requirement for Iddq testing is that all current spikes in the circuit due to switching activity should die down n 1–10 ms is sufficient time for this purpose n On-chip & off-chip current measurement techniques

27. On-chip current sensor

28. Limitations of on-chip sensors n Circuit partitioning requirement significantly increases design complexity n Multiple on-chip sensors. For large IC’s, one on-chip sensor is inadequate and multiple sensors result into significant hardware overhead n A permanent loading on circuit power supply. Due to increased parasitic and loading, on-chip sensor result into significant performance penalty even during normal operation of the circuit

29. Off Chip Current Measurements Problem with insertion inductance

30. Off Chip Current Measurements

31. Summary n I DDQ tests improve reliability, find defects causing:  Delay, bridging, weak faults  Chips damaged by electro-static discharge n No natural breakpoint for current threshold  Get continuous distribution – bimodal would be better n Conclusion: now need stuck-fault, I DDQ, and delay fault testing combined n Still uncertain whether I DDQ tests will remain useful as chip feature sizes shrink further