1. ECE 368 Simple VHDL Synthesis Examples Shantanu Dutt ECE Dept. Univ. of Illinois at Chicago

2. If-then-else synthesis if cond1 then Block_1 elsif cond2 then Block_2 elsif cond3 then Block3 ……. else Block_n Block_1 cond1 Mux Current o/ps I/Ps Block_2 cond2 Mux I/Ps Block_3 cond3 Mux I/Ps Block_n Mux I/Ps Combinational Synthesis – Expensive, High Power but Fast A lower power variation also possible where I/Ps to blocks come via transparent latches that are enabled by the same bits that are selects for the corresponding muxes This avoids signal transitions (that cause dynamic power consumption) in blocks that do not need to be executed. Also, power gating can be used where the Vdd to only that block is enabled for which the mux is enabled; Vdd to all other blocks is “turned off”. Datapath when cond1=false and cond2=true Final o/p of if-then-else sequence Daisy-chain structure + + + I0I0 I1I1 I0I0 I1I1 I0I0 I1I1 I0I0 I1I1 Mux

3. If-then-else synthesis (contd) if cond1 then Block_1 elsif cond2 then Block_2 elsif cond3 then Block3 ……. else Block_n Sequential Synthesis – Slow, but Inexpensive (reuse of FUs) and Low Power Decode cond1 ~ cond1 & cond2 ~ cond1 & ……… & ~ cond_n-1 & cond_n Sequence of states for executing the different blocks by controlling the datapath via control signals Block1 exec. Block 2 exec. Block n exec. Register File 1 ALU 1 Register File 2 ALU 2 Register File k ALU k Datapath Range of options: k=1 is slowest:most “sharing” of resources/FUs  thus least parallelism but least expensive k = max # of parallel operations in any of the n blocks is fastest but most expensive, but less than fully combinational approach as there is FU sharing between blockd E.g., will need at most 2 adders if there are at most 2 parallel additions in any block, and will need at least 1 adder (this will sequentialize any 2 parallel additions in a block) With any level of FU sharing need an FSM controller to orchestrate sharing and timing of different operations and register loads. State for seq. statement foll. If-then-else

4. Case statement synthesis case expression is when choice1 => Block_1 when choice2 => Block_2 ……. when others => Block_n end case; Combinational Synthesis – Expensive, High Power but Fast Faster than if-then-else synthesis if the larger Case mux uses 2-level logic or the large Mux is designed using D&C using 2:1 Muxes. In the latter case, we get a (log n)-delay synthesis versus n-delay in the case of if-then-else, where n = # of choices in a case statement or n = (# of conditions/blocks incl. final “else”, if any) in an if-then-else statement Can also do a low power version where only the selected block will process I/Ps via transparent latches enabled by the choice-logic o/ps (only one set of set of latches will be enabled corresponding to the block to be selected) and/or will have its Vdd enabled. Can also do a less expensive (and low power) version which is partially sequential and controlled by an FSM as in the if-then-else statement Mux Block_1 I/Ps Block_2 I/Ps Block_n I/Ps Final o/p of case statement choice1 I/Ps (expression value) choice2 others Encoder (n: log n) select signal Datapath when choice 2 is activated Mutually exclusive (by defn. of “case” st.)

5. Wait Statement Synthesis Issues wait until (X=‘1’); Next action; Note: Syn. Design Compiler/Vision does not synthesize this wait statement x != 1 x=1 Next action wait until (X’event and X=‘1’); Next action; DxDx 1 QxQx X Q x != 1 Q x =1 Reset X =1 Next action possible synthesis poss. synth. Reset X

6. Wait Statement Synthesis Issues wait for some_time; no synth Cannot be synthesized. In order to describe a similar “wait-for-time effect” that can be synthesized, you need to describe it as an FSM state that self-loops until a counter (set or reset at an earlier state) reaches a count vaue that translates to the desired wait time needed (this will be based on the clock speed). Cntr != 0 Cntr=0 Next action Cntr=n cntr_en=1 Cntdn=1 cntr_en=1 [Cntr <- n] [Cntr <- Cntr-1] = wait for n+2 cc’s;

7. Control Loops for loops, while loops, etc. can be synthesized as “looping FSMs” controlling a datapath Example: R2 := 0; R1 := X; AC = 1; While (AC < 100000) loop R2 := R2 + R1; AC := AC*R2; End loop; Synthesizing a for loop w/ n iterations: Initialize counter & then check its value after counting up every “iteration” of the FSM’s loop (or count down from an initial value of n and check for 0) + R2 R1  AC Comparator 10 5 LT ld_r1 ld_r2 ld_ac Initialize State (AC, R1, R2, etc.) Test State ld_r2 = 1 [R2 <- R2+R1] LT = 1 ld_ac = 1 [AC <- AC*R2] LT = 0 State after while loop LT = 1  AC < 10 5 LT = 0  AC > 10 5 FSM for while loop; assumes 1 cc for each FU operation: Datapath for statements In while loop: