1. Lab 5 :JK Flip Flop and Counter Fundamentals:
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Three stage ripple counter.
Slide 3
Down Counters.
Slide 4
Slide 5
Up/Down Counters.
Slide 6
Altera 4count Symbol.
Slide 7
Cascading 4count Symbols.
Slide 8
BCD Numbers.
Slide 9
Frequency Division
Slide 10
Frequency Division and the UP-1 board.

2. Lab 5: The JK Flip Flop :
The JK flip flop is an improved SR flip flop. The improvement is the replacement of the Ambiguous mode with the Toggle mode. The Set, Reset and No Change modes are still used. The JK flip flop in the example has a negative edge triggered clock. 1 J K Q J K Q
>Clk
No Change
Reset or Kill
To help remember the RESET mode you can think of “K=1” means KILL the output.
To help remember the SET mode you can think of “J=1” means the output will JUMP high.
Set or Jump
Toggle
J=1 and K=1 is called the TOGGLE mode. The AMBIGUOUS mode has been removed.
TOGGLE = Change the output logic level. -If Q starts at 0 then Q will toggle high. -If Q starts at 1 then Q toggle low.
If you study the construction diagram of the JK flip flop you can see how the TOGGLE mode works.
Begin by connecting J=K=1. TOGGLE Mode. S R Q
>Clk J K
Assume Q =0 is the initial condition 1 1 1 1
Trace the logic levels back through the AND gates. 1
Write the logic levels at the output of the AND gates. 1
Inside the JK flip flop there is an SR flip flop ready to set the output to logic 1 when the clock is asserted. Proceed and you will see the output Q toggle and you will also see how the internal SR is setup to toggle again if a second clock pulse was asserted.
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3. Lab 5 : Three Stage Ripple counter :
JK flip flops connected in the toggle mode can be connected together to create a binary counter system. Start with one JK flip flop, apply a clock waveform and sketch the Q output response. Assume PRE and Clr has been disabled (=1) on all flip flops.
Input J K Qa
>Clk 1 J K Qb
>Clk 1 J K Qc
>Clk 1 Qc Qb Qa In 1 2 3 4 5 6 7 1 2 3 4 5 6 7 Qa 1 1
Qa will toggle on each negative edge of the input clock. Qb 1
Connect a second stage to output Qa.
Qb will toggle on each negative edge of Qa. 1 Qc 1
Qc will toggle on each negative edge of Qb.
Connect a third stage to output Qb. 1 1
Label the input clock pulses from 0 to 7 and place the counter response in a table.
The table is called a COUNT state table. The counter is called a MOD 8 counter because it has 8 different count states. The counter restarts at 0, 0, 0 after clock input 7. MOD is short for the word MODULUS.
Connect the flip flop outputs to 3 LED’s and you will see a binary count sequence from 0 … to … 7.
The speed at which the counter counts is controlled by the input clock. 1 PPS input clock will display the 0 to 7 count sequence on the LED’s in 8 seconds. Each count state would last 1 sec. If the clock input was 1000 PPS then all 3 LED’s would appear to be constantly on at the same time. A count cycle would take 8milliSec. Too fast to be visible on the 3 LED’s.
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4. Lab 5: Down Counters :
To make a counter count backwards all you need to do is to connect the Q to the Clk of the next flip flop. J K Qa
>Clk 1 Qb Qc
Input Qc Qb Qa In 1 2 3 4 5 6 7
Qa toggles on every negative edge of the input clock. Qa 1 1 Qb
Qb toggles on every negative edge of Qa. 1 Qa
A negative edge on Qa is the same as the positive edge Qa. 1
Qc toggles on every negative edge of Qb. Which is the same as the positive edge of Qb. Qc 1 1 1
If you place the count states in a table you can see the down count sequence.
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5. Lab 5: Up/Down Counter :
This system combines the features of both an up and a down counter. The system has a count direction control input to select up counting or down counting. J K Qa
>Clk 1 Qb Qc
Up/Down 1 1
Qa•1
Qb•1
Qa•1
Qb•1
When the control input is low, the top AND gates will pass the logic levels from the Q outputs.
The bottom AND gates output 0. The OR gate outputs a Q•1+0 = Q. This connects Q to clock and the counter counts up or forward.
When the control input is high, the bottom AND gates pass the logic levels from the Q outputs.
The top AND gates output 0. The OR gate outputs a Q•1+0 = Q. This connects Q to clock and the counter counts down or backwards.
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6. Lab 5: Altera 4Count Symbol:
The Altera 4count symbol can be found in the mf library. It is very similar to a VHDL binary counter. Apply a pulse waveform to the positive edge triggered clock input and it counts from 0 to 15.
Synchronous Load: LDN and ABCD and Clock:
LDN=0 loads a number into Qa, Qb, Qc, Qd from A, B, C, D on positive edge of clock.
LDN=1 disables the load feature. Clock is used for counting.
The animation will demonstrate how to load the number 6 into the counter.
Step 1: Disable load and clear inputs 1 6
Step 1: Assert load and place number at inputs 1 6
Step 1: Place number at inputs
Step 2: Enable up counting
Step 4: Enable down counting
Step 5: Apply 4 clock pulses
Step 3: Apply 4 clock pulses
LDN A B C D
CIN
DNUP
CLRN
CLK
SETN QA QB QC QD
COUT
4count 1
Asynchronous Load: SETN and ABCD:
SETN=0 loads a number into Qa, Qb, Qc, Qd from A, B, C, D immediately. The clock is not required.
SETN =1 disables the load feature. Clock is used for counting.
The animation will demonstrate how to load the number 6 into the counter. 1
Step 2: Assert SETN
Assert CLRN
Asynchronous Clear: CLRN:
CLRN=0 resets (clears) Qa=Qb=Qc=Qd =0. Clock not required
CLRN =1 disables the clear feature. Clock is used for counting.
Step 2: Assert Clock
Count Direction: DNUP:
DNUP=0 Counter counts forward or up (0,1,2…). DNUP=1 Counter counts backwards or down (15,14,13…).
The animation will demonstrate an up count sequence to 4 and then a down count sequence back to 0. The count sequence can be reversed at any time.
CIN and COUT:
Carry in and Carry out are used to cascade counter symbols. Cascading will be explained in an upcoming lab.
Altera Default Values: Altera connects LDN, SETN, CLRN, DNUP and CIN to 1 if they are left unconnected in a drawing. These are called default values. The default values will make the counter count down and disable the loading and clearing functions.
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7. Lab 5: Cascading 4count Symbols:
Two 4count symbols can be cascaded to create an 8-bit counter system. CIN and COUT are carry input and carry output. They are used to cascade stages.
One 4count symbol is a Mod 16 counter. (0 … 15). Two 4count symbols is Mod 256 (16x16).
LDN A B C D
CIN
DNUP
CLRN
CLK
SETN QA QB QC QD
COUT
4count
LDN A B C D
CIN
DNUP
CLRN
CLK
SETN QA QB QC QD
COUT
4count 1
Connect COUT to CIN. Connect the clocks together. COUT is the carry output. It is 0 when the count is 0 to 14. It is 1 when the count is 15. A carry out is generated at 15 because the counter is about to recycle back to 0. CIN is the carry input. The counter counts at every positive edge of the clock when CIN=1. The counter holds if CIN=0. CIN=1 is the default value if the input is not connected.
It takes 14 clock pulses to cycle the first counter from 0 to 14. During this time COUT =0 and because the second counter has CIN =0 it does not count.
On the next clock pulse, the first counter reaches 15 and then changes COUT to 1.
On the next clock pulse, the first counter cycles back to 0 and the second counter counts to 1 because CIN was 1. COUT then changes back to 0.
The 8-bit counter system cycles the first 4count symbol’s bits from 0 to 15 continuously. The second 4count symbol only counts when there is a carry out signal from the first stage. It takes 256 clock pulses to completely cycle the counter from 0 to 255.
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8. 4 bit numbers for 10, 11, … 15 are not used!
Lab 5: BCD Numbers :
A BCD number is a Binary Coded Decimal number. It is a 4 bit code used to represent the decimal numerals 0, … 9. The 4 bit numbers above 9 are not used in this number system.
Converting decimal to BCD: Example: convert 25 to BCD
Convert each decimal numeral to BCD.
4 bit numbers for 10, 11, … 15 are not used! 2 4 8 1 =0 2 5 =1
0010
0101 =2
Thus 25 = BCD =3 =4
Converting BCD to decimal :
Example: convert BCD to decimal. Start at the BCD point and group BCD bits into blocks of four. Convert each block into a BCD number. =5 =6 =7 =8 7 9 =9 1
Thus BCD = 197
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9. 1 Second 8 PPS 1 PPS 8 PPS 4 PPS 2 PPS 1 PPS
Lab 5 : Frequency Division:
Frequency of a pulse waveform is its pulse rate. A counter halves the frequency of the input clock at each of its outputs.
1 PPS
8 PPS J K Qa
>Clk 1
Input Qb Qc 2 3 4 5 6 7
8 PPS
4 PPS
2 PPS
1 PPS
Mod 8 counter is also called a divide by 8 counter
1 Second
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10. Visible on LED’s! Lab 5 : Frequency Division and the UP board:
The UP-1 board has a 25,1275,000 PPS oscillator. Connecting a counter to a set of LED’s and clocking the counter at this fast rate would result in a count that would not be distinguishable on the LEDS. All LED’s would appear to be on at the same time.
Oscillator
25,175,000 PPS
UP-1
>CLK QA QB QC QD
Connecting the UP oscillator to a 24 stage counter will divide the frequency down to a rate that is distinguishable on LED’s. Grouping any 4 adjacent outputs creates a MOD 16 counter. Each MOD 16 counter group counts a slower speed.
The counter requires 16 clock pulses to count from 0 to 15. Each second the oscillator generates 25,175,000 pulses. LED’s are changing so fast that they all appear to be on at the same time.
Oscillator
25,175,000 PPS
UP-1
>CLK Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
Q10
Q11
Q12
Q13
Q14
Q15
Q16
Q17
Q18
Q19
Q20
Q21
Q22
Q23
Q24
Mod 16counter with a 25,175,000 PPS clock rate.
Mod 16 counter with a 12,587,500 PPS clock rate.
Mod 16 counter with a 6,293,750 PPS clock rate.
Mod 16 counter with a 3,146,875 PPS clock rate.
Pulse rates must be less than 30 PPS in order to be distinguishable on LED’s.
24 PPS
12 PPS
6 PPS
3 PPS
1.5 PPS
0.75 PPS
Visible on LED’s!
Mod 16 counter with a 48 PPS clock rate.
Mod 16 counter with a 24 PPS clock rate.
Mod 16 counter with a 12 PPS clock rate.
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