1. Unit 11 Latches and Flip-Flops Ku-Yaw Chang canseco@mail.dyu.edu.tw Assistant Professor, Department of Computer Science and Information Engineering Da-Yeh University

2. 22004/05/03Latches and Flip-flops Outline 11.1Introduction 11.2Set-Reset Latch 11.3Gated D Latch 11.4Edge-Triggered D Flip-Flop 11.5S-R Flip-Flop 11.6J-K Flip-Flop 11.7T Flip-Flop 11.8Flip-Flops with Additional Inputs 11.9Summary

3. 32004/05/03Latches and Flip-flops Flip-Flops with Additional Inputs Additional inputs to set the flip-flops to an initial state independent of the clock Clear input ClrN Clear input ClrN Q = 0 Preset input PreN Preset input PreN Q = 1 Active-low Active-low a logic 0 is required to clear or set the flip-flop

4. 42004/05/03Latches and Flip-flops Flip-Flops with Additional Inputs CkDPreNClrN Q+Q+Q+Q+ xx00 (not allowed) xx011 xx100 0110 1111 0,1,  x11 Q (no change)

5. 52004/05/03Latches and Flip-flops Timing Diagram for D Flip-Flop with Asynchronous Clear and Preset

6. 62004/05/03Latches and Flip-flops D Flip-Flop with Clock Enable Driven by a common clock Hold existing data even though the data input may be changing Hold existing data even though the data input may be changing

7. 72004/05/03Latches and Flip-flops Outline 11.1Introduction 11.2Set-Reset Latch 11.3Gated D Latch 11.4Edge-Triggered D Flip-Flop 11.5S-R Flip-Flop 11.6J-K Flip-Flop 11.7T Flip-Flop 11.8Flip-Flops with Additional Inputs 11.9Summary

8. 82004/05/03Latches and Flip-flops Summary Q + = S + R’Q (SR=0) Q + = GD + G’Q Q + = D Q + = D · CE + Q · CE’ Q + = JQ’ + K’Q Q + = T  Q = TQ’ + T’Q (SR latch or flip-flop) (gated D latch) (D flip-flop) (D-CE flip-flop) (J-K flip-flop) (T flip-flop)

9. 92004/05/03Latches and Flip-flops Homework #4 1.11.1 2.11.2 3.11.3 4.11.4 5.11.5 6.11.6 7.11.7 8.11.8 9.11.9 Paper Submission, due on May 13, 2004. Late submission will not be accepted.