1. ID 311C:Utilizing JTAG / boundary scan and JTAG emulation for board and system level test and design verification Get the total Coverage ! GOEPEL Electronics Heiko Ehrenberg Managing Director NA Operations 12 October 2010 Version 1.3

2. 2 Heiko Ehrenberg Managing Director of North American Operations at GOEPEL Electronics LLC at Austin, TX responsible for GOEPEL's operations in the USA, Canada, and Mexico providing support and consulting services to North American clients GOEPEL was founded in 1991 and has ~160 employees worldwide, active in JTAG/boundary scan, AOI, AXI, and Functional Test Prior Experience: Field Application Engineer for JTAG/boundary scan supporting GOEPEL customers in Germany and then Europe BSEE from the University of Applied Sciences at Mittweida, Germany

3. 3 Renesas Technology and Solution Portfolio Microcontrollers & Microprocessors #1 Market share worldwide * Analog and Power Devices #1 Market share in low-voltage MOSFET** Solutions for Innovation ASIC, ASSP & Memory Advanced and proven technologies * MCU: 31% revenue basis from Gartner "Semiconductor Applications Worldwide Annual Market Share: Database" 25 March 2010 **Power MOSFET: 17.1% on unit basis from Marketing Eye 2009 (17.1% on unit basis).

4. 44 Renesas Technology and Solution Portfolio Microcontrollers & Microprocessors #1 Market share worldwide * Analog and Power Devices #1 Market share in low-voltage MOSFET** ASIC, ASSP & Memory Advanced and proven technologies * MCU: 31% revenue basis from Gartner "Semiconductor Applications Worldwide Annual Market Share: Database" 25 March 2010 **Power MOSFET: 17.1% on unit basis from Marketing Eye 2009 (17.1% on unit basis). Solutions for Innovation

5. 55 Microcontroller and Microprocessor Line-up Superscalar, MMU, Multimedia  Up to 1200 DMIPS, 45, 65 & 90nm process  Video and audio processing on Linux  Server, Industrial & Automotive  Up to 500 DMIPS, 150 & 90nm process  600uA/MHz, 1.5 uA standby  Medical, Automotive & Industrial  Legacy Cores  Next-generation migration to RX High Performance CPU, FPU, DSC Embedded Security  Up to 10 DMIPS, 130nm process  350 uA/MHz, 1uA standby  Capacitive touch  Up to 25 DMIPS, 150nm process  190 uA/MHz, 0.3uA standby  Application-specific integration  Up to 25 DMIPS, 180, 90nm process  1mA/MHz, 100uA standby  Crypto engine, Hardware security  Up to 165 DMIPS, 90nm process  500uA/MHz, 2.5 uA standby  Ethernet, CAN, USB, Motor Control, TFT Display High Performance CPU, Low Power Ultra Low Power General Purpose

6. 6 Notes continued from previous page (continued from notes section of previous page) Renesas knows that to best facilitate the further growth and success of ubiquitous computing, we cannot offer just one CPU core or a single family of microcomputers. Thus, taking advantage of the broad span of leading technologies we have built up, we have decided to concentrate our future R&D efforts on five major CPU cores capable of excelling at major elements of the huge task. Each is optimized for addressing the requirements of diverse sets of key applications. With that business plan in mind, allow me to explain the relative positioning of these five architectures within our strong portfolio of MCUs and MPUs. An important design trend in recent years has seen system engineers taking full advantage of all the computing power that IC makers have made available — often right up to the limits of project constraints. As a result, there have been more and more design-ins of chips with 32-bit architectures. Renesas now has three complementary 32-bit microcontroller and microprocessor families aiding that trend. At the top end of the features-and-capability spectrum we offer the devices in the SuperH family, a superscalar RISC architecture that executes two instructions per clock cycle. Devices in the SuperH family deliver up to 1200 DMIPS performance, so they’re ideal for and popular in multimedia, Real-time industrial-control, server, and automotive engine-control applications. We also recommend them for performing video and audio processing on Linux-based systems Our second series of 32-bit system design solutions is the V850 family, which today is the top-selling line of 32-bit microcontrollers, worldwide. The V850 architecture provides high performance (up to 500 DMIPS), yet consumes low power while doing so. System designers have found these devices to be particularly well suited for automotive applications. The lower-frequency V850 chips are optimized for low power. Thus, they are excellent choices for portable medical equipment, for example.

7. 77 Microcontroller and Microprocessor Line-up Superscalar, MMU, Multimedia  Up to 1200 DMIPS, 45, 65 & 90nm process  Video and audio processing on Linux  Server, Industrial & Automotive  Up to 500 DMIPS, 150 & 90nm process  600uA/MHz, 1.5 uA standby  Medical, Automotive & Industrial  Legacy Cores  Next-generation migration to RX High Performance CPU, FPU, DSC Embedded Security  Up to 10 DMIPS, 130nm process  350 uA/MHz, 1uA standby  Capacitive touch  Up to 25 DMIPS, 150nm process  190 uA/MHz, 0.3uA standby  Application-specific integration  Up to 25 DMIPS, 180, 90nm process  1mA/MHz, 100uA standby  Crypto engine, Hardware security  Up to 165 DMIPS, 90nm process  500uA/MHz, 2.5 uA standby  Ethernet, CAN, USB, Motor Control, TFT Display High Performance CPU, Low Power Ultra Low Power General Purpose JTAG / boundary scan and JTAG emulation for board and system level test and design verification

8. 88 Innovation IEEE 1149.x JTAG / boundary scan On-Chip / In-Circuit Emulation Functional test Design verification and prototyping Manufacturing test and debug End of line (system) test Field service / warranty/repair IEEE 1149.x (JTAG / boundary scan) + On-Chip Emulation Functional test IEEE 1149.x

9. 9 Intelligent boundary scan solutions GOEPEL is a technology leader in JTAG / boundary scan – creating new, innovative ways to extend the reach of boundary scan beyond pure structural test applications.

10. 10 Agenda Benefits and limitations of IEEE Std. 1149.1 for board level debug and test Overview of board and system level JTAG/boundary scan applications Utilization of On-Chip Emulation resources for board level connectivity test applications Interlaced JTAG Emulation and boundary scan testing Summary of fault coverage improvements and other benefits

11. 11 Key Takeaways By the end of this session you will be able to: Identify potential board and system level test applications supported by JTAG/boundary scan on specific board/system designs; Discuss potential test strategies involving JTAG/boundary scan with test engineering / production test groups

12. 12 JTAG / boundary scan in a nutshell 12

13. 13 Boundary scan test applications /TRST TCK TMS TDI Digital Core Logic Digital Core Logic TDO TAP Controller BPBP BPBP ID Reg IR /TRST TCK TMS TDI Digital Core Logic Digital Core Logic TDO TAP Controller BPBP BPBP ID Reg IR /TRST TCK TMS TDI TDO Bi-Dir Buffer Bi-Dir Buffer R R R AND Gates AND Gates SRAM R

14. 14 JTAG / boundary scan limitations... Strictly digital test access (exception: IEEE 1149.4) Quasi-static tests (low I/O toggle rate), limited dynamic test capabilities (exception: BIST) Test access determined by BScan capabilities implemented in devices on the UUT BScan test coverage could be improved: if test points or connector pins are accessed with Tester I/O by accessing analog circuitry with Tester resources by utilizing On-Chip Emulation and Tester resources for dynamic, quasi-functional tests

15. 15 ✓ Structural Test ✓ Efficient ATPG tools ✓ Pin Level Diagnostics ✓ In-System Test / Programming - Flash programming inefficiencies - Limits in dynamic test - Complexity of cluster tests - Need for BScan Register ✓ Functional Test ✓ Fault Coverage ✓ At-Speed Test ✓ FLASH programming speed - µP/µC specific pods - Limited ATPG - Quality of diagnostics - Limited In-System Test / Programming How to get the best of both worlds? Boundary scan vs. Emulation

16. 16 ✓ Structural Test ✓ Efficient ATPG tools ✓ Pin Level Diagnostics ✓ In-System Test / Programming - Flash programming inefficiencies - Limits in dynamic test - Complexity of cluster tests - Need for BScan Register ✓ Functional Test ✓ Fault Coverage ✓ At-Speed Test ✓ FLASH programming speed - µP/µC specific pods - Limited ATPG - Quality of diagnostics - Limited In-System Test / Programming On-Chip Programming + Interlaced Emulation Test VarioTAP

17. 17 Classification of boundary scan applications

18. 18 Utilization of On-Chip Emulation resources for board level connectivity test applications

19. 19 JTAG Generic μP / MCU / CPU model (On-Chip Resources) Emulation Test Bus IF Type A Bus IF Type A Bus IF Type X Bus IF Type X Internal Circuits Internal Circuits Analog I/O Digital I/O Mixed I/O Flash System Bus IF Core Application Type A: Programming Functions for On-Chip or external Flash Application Type A: Programming Functions for On-Chip or external Flash Application Type B: Bus Control Functions for Bus Emulation Test Application Type B: Bus Control Functions for Bus Emulation Test Application Type C: Test Functions for On-Chip Resources Application Type C: Test Functions for On-Chip Resources On-Board Resources: DRAM, External Periphery, Bridges, etc. PCI Express, CAN, LIN, Flexray, BlueTooth, WLAN, USB, LAN, RS232,... Audio, Video, Legacy analog, Legacy digital, PWM signals, I2C, SPI, μW,...

20. 20 TAP Flash ISP Standard I/FLAS Standard I/FLASH Flash Bridge Standard I/RAM RAM Standard I/I/O I/O JTAG Bus IF Type A Bus IF Type A Bus IF Type X Bus IF Type X Internal Circuits Internal Circuits Analog I/O Digital I/O Mixed I/O Flash System Bus IF Core JTAG Standard I/O JTAG PHY Signal Conditioning

21. 21 TAP Bus Emulation Test JTAG Bus IF Type A Bus IF Type A Bus IF Type X Bus IF Type X Internal Circuits Internal Circuits Analog I/O Digital I/O Mixed I/O Flash System Bus IF Core Standard I/O Bridge Standard I/FLAS Standard I/FLASH Flash Standard I/RAM RAM Standard I/I/O I/O JTAG PHY Signal Conditioning JTAG External Tester Channels

22. 22 TAP System Emulation Test JTAG Bus IF Type A Bus IF Type A Bus IF Type X Bus IF Type X Internal Circuits Internal Circuits Analog I/O Digital I/O Mixed I/O FLASH System Bus IF Core Standard I/O Bridge Standard I/FLAS Standard I/FLASH FLASH Standard I/RAM RAM Standard I/I/O I/O JTAG PHY Signal Conditioning JTAG External Tester Channels

23. 23 Emulation Tool suite for Flash ISP and Testing CASLAN Source code Bscan instruction VarioTAP Instruction Bscan Instruction Executable Available VarioTAP Commands Selected Device Library Device Model #1 -- Register descriptions -- Port descriptions -- ……. Device Model #2 -- Register descriptions -- Port descriptions -- ……. -- VarioTAP Model Device Model #n (µP) -- Register descriptions -- Port descriptions -- … -- VarioTAP Model(s) SYSTEM CASCON™ Environment µP/µC specific models are the key for VarioTAP Access to VarioTAP functions via CASLAN (high-level commands) Compiler VarioTAP application development

24. 24 VarioTAP applications Test of Digital I/O Test of Analog / Mixed-Signal I/O Fast external Flash Programming On-Chip Flash Programming Test of Bus Interfaces Test of Peripheral Circuitry Dynamic Memory Access Tests Customer specific Tests Unique: Interlaced utilization of emulation resources and boundary scan resources

25. 25 Fault coverage improvements and other benefits Boundary scan provides: Embedded test access Deterministic test coverage Very good diagnostics JTAG (on-chip) emulation provides: Dynamic fault coverage Verification of circuit functions

26. 26 Fault coverage improvements and other benefits VarioTAP combines boundary scan and on-chip emulation to provide: JTAG controlled functional tests Interlaced boundary scan and on-chip emulation tests for extended connectivity tests Automated test generation and deterministic test coverage for (functional) on-chip emulation tests

27. 27 Questions?

28. 28 Question 1 Is there a standard defining JTAG / boundary scan resources? If so, which standard? Yes: IEEE 1149.1 Also: IEEE 1149.4, IEEE 1149.6, IEEE 1149.7

29. 29 Question 2 Name potential board and system level test applications supported by JTAG / boundary scan. Infrastructure test Interconnect test Memory access (cluster) test Logic cluster test In-system programming for Flash, sEEPROM, CPLD …

30. 30 Question 3 What is one of the most important printed circuit board level “design for test” requirements enabling the utilization of boundary scan capabilities implemented in integrated circuits? Implement a boundary scan chain ! Make the TAP accessible. Allow Compliance enable pattern to be satisfied to enable JTAG / boundary scan compliance.

31. 31 Feedback Form Please fill out the feedback form! If you do not have one, please raise your hand

32. 32 Thank You!

33. 33 For further information, please: Visit our website at www.goepelusa.comwww.goepelusa.com Contact your local sales representative Call us at 1-888-4GOEPEL Email us at sales@goepelusa.comsales@goepelusa.com Contact information

34. 34 Appendix

35. 35 References and tools White Paper: “Combining Boundary Scan and JTAG Emulation for advanced structural Test and Diagnostics” Boundary Scan Coach: software tool demonstrating the key principles of JTAG / boundary scan as defined in IEEE 1149.1 BSDL Syntax Checker: software for verification of BSDL syntax and semantics TAP Checker: software for validation of JTAG / boundary scan implementations in integrated circuits CASCON GALAXY: software for device, board, and system level JTAG / boundary scan test and emulation applications