1. What is shift register?
A shift register is a digital memory circuit found in calculators, computers, and data-processing systems. Bits (binary digits) enter the shift register at one end and emerge from the other end. The two ends are called left and right. Flip flops, also known as bistable gates, store and process the data. 1

2. Applications of shift registers
Computer and Data Communications
Serial and Parallel Communications
Multi-bit number storage
Sequencing
Basic arithmetic such as scaling (a serial shift to the left or right will change the value of a binary number a power of 2)
Logical operations 2 2

3. Parallel versus Serial
Serial communications: provides a binary number as a sequence of binary digits, one after another, through one data line.
Parallel communications: provides a binary number as binary digits through multiple data lines at the same time. 3

4. Shift Registers
Shift Registers are devices that store and move data bits in serial (to the left or the right),
..or in parallel,
..or a combination of serial and parallel. 4

5. Ideally, in shift registers, the binary digit transfers (shifts) from the output of one flip-flop to the input of the next individual Flip-Flop at every clock edge.
Once the binary digits are shifted in, the individual Flip-Flops will each retain a bit, and the whole configuration will retain a binary number. 5

6. Construction of shift regiters
Shift registers are constructed from flip-flops due to their characteristics:
Edge-triggered devices
Output state retention
Each Flip-Flop in a shift register can retain one binary digit.
For instance, if a 5-bit binary number needs to be stored and shifted, 5 flip-flops are required.
Each binary digit transfer operation requires a clock edge.
Asynchronous inputs are useful in resetting the whole configuration. 6

7. Example of shift register construction
Shift registers are comprised of D Flip-Flops that share a common clock input.
D Q Q 7

8. Possible combinations of Data Transfer Methods
SISO: Serial In, Serial Out
SIPO: Serial In, Parallel Out
PISO: Parallel In, Serial Out
PIPO: Parallel In, Parallel Out 8

9. SISO Flip-Flop Shift Register
a Serial In Serial Out shift register has a single input and a single output
D Q Q
Input
Output 9

10. SIPO Flip-Flop Shift Register
a Serial In Parallel Out shift register has a single input and access to all outputs
D Q Q
Input
Output 10

11. PISO Flip-Flop Shift Register
a Parallel In Serial Out shift register requires additional gates, and the parallel input must revert to logic low.
Input
D Q Q
Output 11

12. PIPO Flip-Flop Shift Register
a Parallel In Parallel Out register has the simplest configuration. It represents a memory device.
D Q Q
Input
Output 12

13. Universal Shift Registers
Universal Shift Registers can be configured to operate in a variety of modes. For instance, they can be configured to have either Serial or Parallel Input/Output. 13

14. JK Shift Registers
J-K Shift registers are seldom used, as two inputs (J,K) are required to load the first flip-flop (note all others receive only set or reset inputs).
Input
Output
J Q
K Q 14

15. Introduction: Counters
Counters are circuits that cycle through a specified number of states.
Two types of counters:
synchronous (parallel) counters
asynchronous (ripple) counters
Ripple counters allow some flip-flop outputs to be used as a source of clock for other flip-flops.
Synchronous counters apply the same clock to all flip-flops.

16. Asynchronous (Ripple) Counters
Asynchronous counters: the flip-flops do not change states at exactly the same time as they do not have a common clock pulse.
Also known as ripple counters, as the input clock pulse “ripples” through the counter – cumulative delay is a drawback.
n flip-flops  a MOD (modulus) 2n counter. (Note: A MOD-x counter cycles through x states.)
Output of the last flip-flop (MSB) divides the input clock frequency by the MOD number of the counter, hence a counter is also a frequency divider.

17. Asynchronous (Ripple) Counters
Example: 2-bit ripple binary counter.
Output of one flip-flop is connected to the clock input of the next more-significant flip-flop. K J
HIGH Q0 Q1
FF1
FF0
CLK C 4 3 2 1
CLK Q0 Q1
Timing diagram
00  01  10  11 

18. Asynchronous (Ripple) Counters
Example: 3-bit ripple binary counter. K J Q0 Q1
FF1
FF0 C
FF2 Q2
CLK
HIGH 4 3 2 1
CLK Q0 Q1 8 7 6 5 Q2
Recycles back to 0

19. Asynchronous (Ripple) Counters
Propagation delays in an asynchronous (ripple- clocked) binary counter.
If the accumulated delay is greater than the clock pulse, some counter states may be misrepresented! 4 3 2 1
CLK Q0 Q1 Q2
tPLH
(CLK to Q0)
tPHL (CLK to Q0)
tPLH (Q0 to Q1)
tPHL (Q0 to Q1)
tPLH (Q1 to Q2)

20. Asynchronous (Ripple) Counters
Example: 4-bit ripple binary counter (negative-edge triggered). K J Q1 Q0
FF1
FF0 C
FF2 Q2
CLK
HIGH
FF3 Q3
CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Q0 Q1 Q2 Q3

21. Asyn. Counters with MOD no. < 2n
States may be skipped resulting in a truncated sequence.
Technique: force counter to recycle before going through all of the states in the binary sequence.
Example: Given the following circuit, determine the counting sequence (and hence the modulus no.) K J Q
CLK
CLR C B A
All J, K inputs are 1 (HIGH).

22. Asyn. Counters with MOD no. < 2n
Example (cont’d): K J Q
CLK
CLR C B A
All J, K inputs are 1 (HIGH). A B 1 2 C
NAND
Output 3 4 5 6 7 8 9 10 11 12
Clock
MOD-6 counter produced by clearing (a MOD-8 binary counter) when count of six (110) occurs.

23. Asyn. Counters with MOD no. < 2n
Example (cont’d): Counting sequence of circuit (in CBA order). A B C
NAND
Output 1 2 3 4 5 6 7 8 9 10 11 12
Clock 1 1 1 1 1 1
111
000
001
110
101
100
010
011
Temporary state
Counter is a MOD-6 counter.
Asynchronous Counters with MOD number < 2^n

24. Asyn. Counters with MOD no. < 2n
Exercise: How to construct an asynchronous MOD-5 counter? MOD-7 counter? MOD-12 counter?
Question: The following is a MOD-? counter? K J Q
CLR C B A D
E F
All J = K = 1. E F

25. Asyn. Counters with MOD no. < 2n
Decade counters (or BCD counters) are counters with 10 states (modulus-10) in their sequence. They are commonly used in daily life (e.g.: utility meters, odometers, etc.).
Design an asynchronous decade counter. D
CLK
HIGH K J C
CLR Q B A
(A.C)'

26. Asyn. Counters with MOD no. < 2n
Asynchronous decade/BCD counter (cont’d). D
CLK
HIGH K J C
CLR Q B A
(A.C)' D C 1 2 B
NAND
output 3 4 5 6 7 8 9 10
Clock 11 A 1

27. Asynchronous Down Counters
So far we are dealing with up counters. Down counters, on the other hand, count downward from a maximum value to zero, and repeat.
Example: A 3-bit binary (MOD-23) down counter. K J Q1 Q0 C Q2
CLK 1 Q Q'
3-bit binary up counter 1 K J Q1 Q0 C Q2
CLK Q Q'
3-bit binary down counter