1. 1 VLSITECHNOLOGY CHIP DESIGN SILICON PROCESSING – FABRICATION YIELD BY SRITEJA TARIGOPULA SUBMITTED TO DR. ROMAN STEMPROK

2. 2 VLSITECHNOLOGY CHIP DESIGN Overview of Silicon Processing n An integrated circuit (IC) consists of several patterned layers of materials to form FETs and interconnects n In a modern process : – Minimum feature size < 0.12µm – Individual chips with more than 100 million FETs n The techniques needed to fabricate chips of this sophistication have been developed over several decades at tremendous cost

3. 3 VLSITECHNOLOGY CHIP DESIGN Silicon Processing - Wafers n Si ICs are created on large circular sheets of Si called wafers – 100-300mm in diameter – ~ 0.7 mm thick n Si IC is ~ 1 cm on a side – Many ICs on a single wafer n Location of an IC on a wafer is called a die site n A flat on the wafer is used as a reference plane to form a grid for die placement

4. 4 VLSITECHNOLOGY CHIP DESIGN Silicon Processing - Wafers n The manufacturing capacity of a chip factory is measured by the number of wafer starts per week n The number of wafer starts indicates how many “fresh” wafers are introduced into the fabrication sequence n Wafers are processed in groups, and it typically takes several weeks for a lot to pass through the entire processing line

5. 5 VLSITECHNOLOGY CHIP DESIGN Silicon Processing – Fabrication Yield n Not every die site on the Si wafer produces a functional circuit – Due to many factors inherent in the complexity of the Si processing n To quantify problem, chip manufacturers use the concept of fabrication yield Y ; Y = [N G / N T ] x 100% – N G = number of good functional sites – N T = total number of sites on wafer n High yield values are critical for IC economic stability

6. 6 VLSITECHNOLOGY CHIP DESIGN Silicon Processing – Fabrication Yield n Yield analysis is based on predicting the yield Y of a particular IC process – very specialised aspect of VLSI manufacturing – requires thorough understanding of all aspects of Si processing n Yield analysts attempt to optimise Y for a given IC design – work closely with groups on manufacturing line – also work with specialist wafer analysis groups

7. 7 VLSITECHNOLOGY CHIP DESIGN Silicon Processing – Effect of die area on yield n A variable that is critically important to increasing the yield is the area of the die A die n The total die sites N T on a wafer of diameter d is found as : N T =  (d - d e ) 2 / 4A die – d e = wasted edge distance from placing rectangular die onto round wafer n Empirical analysis shows that large area die are plagued by smaller yields

8. 8 VLSITECHNOLOGY CHIP DESIGN Silicon Processing – effect of die area on yield n Defects on the wafer can result in circuit failure and influence Y n The average number of defects per cm 2 is denoted by the parameter D and quantifies the wafer “perfection” – for modern IC production D is typically ~ 1 cm -2 n For isolated defects :Y = exp[-  (A die D)] n For clustered defects :Y = [1 - (A die D)/c] c – c = empirical parameter that characterises cluster structure

9. 9 VLSITECHNOLOGY CHIP DESIGN Silicon Processing – Economic Factors n For economic survival, a Si chip manufacturing plant must be profitable : profit-per-chip = Csell - Cchip is not easy to estimate n n C chip = chip production costs n n C chip includes – – Materials – – personnel salaries (design, manufacture, test etc) – – overheads (electricity, water, taxes etc) – – initial plant commission ~ $1-3 billion !! n n C sell = chip selling price – – all direct and indirect costs – – fraction of plant debt n n C sell must however be at level that customers will pay – – high chip demand  C sell  © © “whatever market will bear” – – low chip demand  C sell  © © Withdraw product?

10. 10 VLSITECHNOLOGY CHIP DESIGN Silicon Processing – Economic Factors n Notice also that C sell tends to decrease with time ! – Hottest new microprocessors eventually become basement bargains – no problem to IC manufacturer provided initial engineering costs are recouped – original IC design can be very expensive n A helpful factor in IC manufacturing profitability is that as time progresses : – C chip  C materials – for CMOS Si is very cheap compared to alternatives such as III-Vs – keeping product lines operative for many years therefore improves overall profitability

11. 11 VLSITECHNOLOGY CHIP DESIGN Refrences & Introduction to VLSI Circuits and Systems, by John P.Uyemura & D.Morgan and K.Board, “An Introduction to Semiconductor Microtechnology”, J.Wiley & Sons, 1988 & http://www.personal.dundee.ac.uk/~dmgoldie/teaching/eg4 013/lectures/1 http://www.personal.dundee.ac.uk/~dmgoldie/teaching/eg4 013/lectures/1 & http://www.stanford.edu/class/ee271/stick_to_layout/stick_ to_layout.html http://www.stanford.edu/class/ee271/stick_to_layout/stick_ to_layout.html

12. 12 VLSITECHNOLOGY CHIP DESIGN Thank you…