1. CS 150 - Spring 2007 – Lec. #11: Course Project - 1 Videoconferencing Project zProject Concept and Background zCheckpoint Structure zBells and Whistles

2. CS 150 - Spring 2007 – Lec. #11: Course Project - 2 Objectives zBroad “brush” overview of the project zDetails will be covered in the lab lectures, starting next week zNOTE: anything discussed in the lab lectures and project checkpoint write-ups supercedes what I describe here! yNeil and Allen have a working implementation of the project yThey know the project better than I do! Listen to them!

3. CS 150 - Spring 2007 – Lec. #11: Course Project - 3 Course Project: Videoconferencing System zNot quite this … but: yVideo camera capture yCRT video display ySerial compressed video 2-way transmission between two stations yWireless communications y(no audio this semester) yImplemented in a Xilinx FPGA on the Calinx boards in the lab yGroups of two -- your Lab #4/#5 partner yCommit to a TA now for grading purposes

4. CS 150 - Spring 2007 – Lec. #11: Course Project - 4 Calinx EECS 150 Lab/Project Protoboard Flash Card & Micro-drive Port Video Encoder & Decoder AC ’97 Codec & Power Amp Video & Audio Ports Four 100 Mb Ethernet Ports 8 Meg x 32 SDRAM Quad Ethernet Transceiver Xilinx Virtex 2000E Seven Segment LED Displays Prototype Area

5. CS 150 - Spring 2007 – Lec. #11: Course Project - 5 Complete Videoconferencing System Display Video Encoder (Checkpoint #1) Video Decoder Camera Videostream Video Decoder Checkpoint #2 Checkpoint #4 SDRAM (Checkpoint #0) Multiport SDRAM Memory System Multiport Arbitration Wireless Transceiver (Checkpoint #3)

6. CS 150 - Spring 2007 – Lec. #11: Course Project - 6 Checkpoint #0/#1/#2: SDRAM Interface zMemory protocols yBus arbitration yAddress phase yData phase zDRAM is large, but few address lines and slow yRow & col address yWait states zSynchronous DRAM provides fast synchronous access current block yLittle like a cache in the DRAM yFast burst of data zArbitration for shared resource

7. CS 150 - Spring 2007 – Lec. #11: Course Project - 7 Checkpoint #1: Video Encoding zPixel Array: yDigital image represented by matrix of values, where each is a function of the information surrounding it in the image; single element in image matrix: picture element or pixel (includes info for all color components) yArray size varies for different apps and costs: some common sizes shown zFrames: yIllusion of motion created by successively flashing still pictures called frames

8. CS 150 - Spring 2007 – Lec. #11: Course Project - 8 Checkpoint #1: Video Encoding zVideo details fairly complex and involve many choices: yNTSC vs. PAL, HDTV, … yInterleaved even-odd frames (TV) vs. progress scan (computer and digital displays) yFrame size, frame rate yPixel encodings: RGB, YUV/YCB (Luminance, Chrominance -- brightness plus color difference signals) ySubsampling to reduce data demands (compression trick) yInputs: ITU-R BT.601 Format (Digital Broadcast NTSC) yOutputs: Component video, S-video to drive LCDs in lab yFortunately, Calinx board has a chip on-board that deals with much of the grungy details …

9. CS 150 - Spring 2007 – Lec. #11: Course Project - 9 ITU-R BT.656 Details zInterfacing details for ITU-601 Pixels per line858 Lines per frame525 Frames/sec29.97 Pixels/sec13.5 M Viewable pixels/line720 Viewable lines/frame487 zWith 4:2:2 chroma sub-sampling, send 2 words/pixel (Cr/Y/Cb/Y) zWords/sec = 27M Encoder runs off a 27MHz clock zControl info (horizontal & vertical synch) is multiplexed on data lines zEncoder data stream show to right zSee video tutorial documents on course documentation web page!

10. CS 150 - Spring 2007 – Lec. #11: Course Project - 10 Checkpoint #1: Video Encoder zDisplay driver processes pixels within frame buffer zDrive ADV7194 video encoder device to output correct NTSC video zGain lots of experience reading data sheets zDictates the 27 MHz operation rate yUsed throughout graphics subsystem

11. CS 150 - Spring 2007 – Lec. #11: Course Project - 11 Calinx On-Board Video Encoder zAnalog Devices ADV7194: ITU 601/656 in, Composite Video Out zSupports: yMultiple input formats and outputs yOperational modes, slave/master yUsed in default mode: ITU-601 as slave s-video output z Digital input side connected to Virtex pins z Analog output side wired to on board connectors or headers z I 2 C interface for initialization: yWired to Virtex

12. CS 150 - Spring 2007 – Lec. #11: Course Project - 12 SDRAM READ Burst Timing

13. CS 150 - Spring 2007 – Lec. #11: Course Project - 13 Checkpoint #2: Video Decode zPretty much the reverse of the encoding process of Checkpoint #1 zWe will provide the base Verilog for video decode zYou will need to integrate video decode with your SDRAM arbitrated write port zIntegrate with your Checkpoint #1

14. CS 150 - Spring 2007 – Lec. #11: Course Project - 14 Checkpoint #3: Wireless Transceiver zThis will involve interfacing to the wireless transceiver chip on the Calinx2 board zNeil working on a clear description of how this works

15. CS 150 - Spring 2007 – Lec. #11: Course Project - 15 Checkpoint Build Up to Complete Project zWeek #7: Lab #6/Checkpoint #0 -- Basic SDRAM Subsystem zWeek #8: Checkpoint #1 -- SDRAM to Video Display (Encoder) zWeek #9: Checkpoint #2 -- Local Video System yVideo Capture (Decoder) to SDRAM to Video Display (Encoder) yVideo Decoder Verilog will be provided to you zWeek #10/11 : Checkpoint #3 -- Wireless Transceiver yMidterm #2 scheduled for Week #10 ySpring break between Week #10 and #11 zWeek #12/13: Checkpoint #4 -- Putting it altogether yVideo Capture to SDRAM to Wireless Transceiver to SDRAM to Video Display zWeek #14: Final Report

16. CS 150 - Spring 2007 – Lec. #11: Course Project - 16 Possible Bells and Whistles zStill thinking about this but here are some ideas: yPerformance tuning: larger remote display, higher refresh rate ySending more data per unit time via compression/decompression through the wireless transceiver yYour good idea here yNOTE: We don’t necessary know how to implement these ourselves! (these haven’t been implemented in the TA solution, for example) yNOTE: There will be a bonus for an early demo of the complete project at the end of Week #12 (one week early) yNOTE: Extra credit will be limited to 20% extra points and no extra credit unless the standard functionality works