1. Lec 17 : ADDERS ece407/507

2. Outline Introduction to Adders Adder Design Types of Adders
Design Aspects
Discussion on Lab 4

3. Adders

4. Full-Adder

5. The Binary Adder

6. Express Sum and Carry as a function of P, G, D
Define 3 new variable which ONLY depend on A, B
Generate (G) = AB
Propagate (P) = A Å B
Delete = A B
Can also derive expressions for S
and C
based on
D and P o
Note that we will be sometimes using an alternate definition for
Propagate (P) = A + B

7. The Ripple-Carry Adder
Worst case delay linear with the number of bits
td = O(N)
tadder = (N-1)tcarry + tsum
Goal: Make the fastest possible carry path circuit

8. Complimentary Static CMOS Full Adder
28 Transistors

9. Inversion Property

10. Minimize Critical Path by Reducing Inverting Stages
Exploit Inversion Property

11. A Better Structure: The Mirror Adder

12. Mirror Adder
Stick Diagram

13. The Mirror Adder
The NMOS and PMOS chains are completely symmetrical. A maximum of two series transistors can be observed in the carry- generation circuitry.
When laying out the cell, the most critical issue is the minimization of the capacitance at node Co. The reduction of the diffusion capacitances is particularly important.
The capacitance at node Co is composed of four diffusion capacitances, two internal gate capacitances, and six gate capacitances in the connecting adder cell .
The transistors connected to Ci are placed closest to the output.
Only the transistors in the carry stage have to be optimized for optimal speed. All transistors in the sum stage can be minimal size.

14. Transmission Gate Full Adder

15. Manchester Carry Chain

16. Manchester Carry Chain

17. Manchester Carry Chain
Stick Diagram

18. Carry-Bypass Adder
Also called Carry-Skip

19. Carry-Bypass Adder (cont.)
tadder = tsetup + Mtcarry + (N/M-1)tbypass + (M-1)tcarry + tsum

20. Carry Ripple versus Carry Bypass

21. Carry-Select Adder

22. Carry Select Adder: Critical Path

23. Linear Carry Select

24. Square Root Carry Select

25. Adder Delays - Comparison

26. LookAhead - Basic Idea

27. Look-Ahead: Topology
Expanding Lookahead equations:
All the way:

28. Logarithmic Look-Ahead Adder

29. Carry Lookahead Trees
Can continue building the tree hierarchically.

30. About Lab 4 Design a 4 bit carry Look Ahead Adder
Measure Propagation Delay
Layout
Simulations
Analysis

31. Layout Focus on a Modular design
ex: Design of propagate and generate blocks
Test individual modules First.Go ahead only if each module works.Modules like
Propagate
Generate
Carry Generator
Hint: Use the gates designed in previous labs.
Take care of area of the designs

32. Simulations
Individual Blocks like Propagate, Generate,carry generator need to be simulated.
Measure the propagation delay of each of the blocks,Area etc.
Simulation of the complete Design
EACH STEP CARRYS POINTS!!!!!

33. Analysis Comment on the design considerations.
Sizing of the Transistors
Reducing Capacitance
Identify the critical path
Design Problems and Solutions.

34. What is to be turned in…
A good report (need not be highly detailed) covering the above aspects.
When….Last day of Classes!!!!
Advice: Start your work soon.Things are not as easy as they seem.

35. Questions