1. Princess Sumaya Univ. Computer Engineering Dept. Chapter 2:

2. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 1 / 18 Basic Computer Organization  The 5 Classic Components of a Computer  The Basic Hardware/Software Interface  The Stored-Program Concept

3. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 2 / 18 Instructions  Assembly Language Instruction: Perform:a = b + c ADDa, b, c; a  b + c What are ‘a’, ‘b’ and ‘c’? ●The storage concept: ♦ Registers (R1, R2 …) ♦ Memory  Sequence of Instructions: Perform: a = (b + c) – (d + e)

4. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 3 / 18 Memory Operands  Data Transfer Instructions ●Memory Address (Location) ●Slower than registers ●Lower bandwidth than registers  Load and Store Instructions 0 1 2 Memory

5. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 4 / 18 Constant Operands  Memory Operand Perform a = b + 4  Immediate Operand Memory b 4 21 22

6. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 5 / 18 Memory Access  Height and Width 1 KB 4 KB  Address & Data 16 Locations  1 K Locations  1 M Locations   Read & Write Memory 4 3 0 1 21 22 1024 8 bit 1 KB

7. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 6 / 18 Stored Program Architecture Instructions (Program) Operands (Data) Memory 1024 x 32 OpcodeOperands Binary Operand

8. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 7 / 18 Memory Organization  Byte Access  Word Access 20 Byte 21 Byte 20 Byte Byte Byte Byte 24 Byte Byte Byte Byte 20 Byte Byte 22 Byte Byte

9. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 8 / 18 Memory Organization  Mixed Access ●Little Endian ●Odd/Even Alignment 20 Byte Byte 22 Byte Byte DATABUS MSB LSB

10. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 9 / 18 Memory Organization  Mixed Access ●Alignment! 20 Byte Byte Byte Byte 24 Byte Byte Byte Byte DATABUS MSB LSB

11. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 10 / 18 Instruction Representation  Instruction Format  Machine Language & Machine Code Sequence of instructions OpcodeOperands ADD R1, R2, 47 5 1 2 2F 01010001001000101111 5 1 2 2 F Assembly Language Machine Language

12. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 11 / 18 Operations (Opcodes)  Arithmetic ●Add, Sub, Mul, Div, Inc, Dec …  Logic ●Shift ♦ Logical & Arithmetic ♦ Right & Left ●Bitwise AND, OR, XOR ●Complement (NOT) 1 0 1 0 0 1 1 1

13. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 12 / 18 Operations (Opcodes)  Shift Operation for Multiplication ●Multiply by 2 ♦ Shift Left 1 bit ♦ Unsigned Binary ♦ 2’s Complement ●Multiply by 10 ♦ BCD ♦ Shift Left 4 bits 0 0 0 0 0 1 0 0 1 1 1 1 1 1 0 1 0 0 0 0 0 1 0 0 1 0 0 1

14. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 13 / 18 Control Instructions  Making Decisions (Conditional Branches) Perform if (i == j) then a = b + c else a = b – c i == j ? a = b + ca = b – c

15. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 14 / 18 Control Instructions  Transferring Execution ●Unconditional Branch or Jump ●Call Subroutine ●Software Interrupt

16. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 15 / 18 RISC & CISC  Reduced Instruction Set Computer ●32-Bit Storage: ♦ Registers (R1, R2 … R31) ♦ Memory ●Arithmetic operations: ♦ Simple ♦ Limited to registers  Complicated Instruction Set Computer ●IA-32

17. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 16 / 18 EAX Intel Architecture IA-32  General-Purpose Registers (GPRs)  Segment Registers Segmented Memory Addressing (Real Mode) ALAX EAX AXAL EBX BXBL ECX CXCL EDX DXDL ESISI EDIDI “Base” “Count” CS SS DS “Division” “String Source” “String Destination” Also: “Accumulator”

18. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 17 / 18 Intel Architecture IA-32  Variable Length Instruction Format

19. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. 18 / 18 Intel Architecture IA-32 YearMicroprocessorAddress BitsData BitsTransistors 197140041242,300 197480801686,000 197880862016/829,000 1982802862416/8134,000 1985803863232/16/8275,000 1989804863232/16/81,200,000 1992Pentium3232/16/83,100,000 1995Pentium Pro3232/16/85,500,000 1997Pentium II3232/16/87,500,000 1999Pentium III3232/16/89,500,000 2001Pentium 43232/16/842,000,000 2004Pentium 4 EM64T6432/16/8125,000,000 2008Core 2 Quad6432/16/8820,000,000

20. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. Chapter 2

21. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. Chapter 2 Exercise 1  Write an assembly language program to perform a+2b where ‘a’ and ‘b’ are stored in R1 and R2.  Write an assembly language program to swap two locations at memory addresses 10 and 20.  Rewrite the following program to run faster: SUB R1, R1, R1 INC R1 ADD R2, R3, R1  A memory has 4 bits of address and 4 bits of data. Determine the total number of bits inside it.

22. Princess Sumaya University 22444 – Computer Arch. & Org. (1) Computer Engineering Dept. Chapter 2 Exercise 2  Determine the value of R1: LD R1, M [ 43 ]  Write the assembly instruction at 44.  Assuming 8-bit registers, determine the value of R1: Load Immediate R1, Binary ‘11110010’ Arith Shift Right R1  Assuming i and j are integers, R1= i and R2 = j, write the C- language statement for: Compare R1, R2 Jump Equal Label_1 Clear R1 Label_1: Clear R2 4000100011010001010000000100010000 4410110001000110100001001000010001 Opcode Operand 1 Operand 2 Operand 3 Add (= B1)Reg (5 bits) Add (= B2)Reg (5 bits) Constant