Power Converters and Drives Lab -a Research Overview

Power Converters and Drives Lab -a Research Overview
Prof. K. Gopakumar Centre for Electronics Design and Technology Indian Institute of Science, Bangalore INDIA: CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA
Conventional two-level inverter structure S1 S3 S5 A1 B1 C1 Vdc S4 S6 S2 Induction motor CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

SVPWM for conventional two-level inverter V bs V V as cs V /2 dc C1 -V /2 dc wt CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Pole voltage waveforms in conventional two-level inverter Reference signals and carrier (wt) v AN BN CN 0.5 -0.5 V a0 b0 c0 dc /2 -V Vt π/2 π 3 π/2 2 π CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Phase voltage waveforms in conventional two-level inverter Phase voltage Phase current CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Presentation outline Multilevel inverters Topologies Inverter topologies cascading two level inverters Inverter topologies with open-end IM drive Inverter topologies with asymmetric DC link voltages Multilevel inverter topologies for common mode voltage elimination Two-level inverter scheme with common mode voltage elimination Higher level of multilevel inverter scheme DC-link capacitor voltage balancing winding induction motor drive Three-level structure with single power supply PWM signal generation for multilevel inverter A Space Phasor Based Self Adaptive Current Hysteresis Controller Multi-phase (six-phase) and multi motor drive Sensorless control scheme for IM drive 12-sided polygonal voltage space phasor generation. CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Multilevel inverters CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Advantages of multilevel inverters over the two-level inverters Synthesis of higher voltage levels using power devices of lower voltage ratings Increased number of voltage levels which leads to better voltage waveforms and reduced Total Harmonic Distortion (THD) in voltage Reduced switching stresses on the devices CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Neutral clamped inverter topology for 3-level inversion + S11 S21 S31 C1 S12 S22 S32 Vdc o A B C 3-ph Ac mains C2 S13 S23 S33 _ S14 S24 S34 The neutral point fluctuates as the capacitors C1 and C2 carry load currents Bulkier capacitors are needed to check the neutral point fluctuation PWM strategies aim to balance the neutral point dynamically CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Dual Inverter fed induction motor with open end winding CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Dual Inverter fed induction motor with open end winding Inverter-I Inverter-II Vdc/4 o a’ a b b’ c c’ Vdc/4 3-ph IM with open wdg. The neutral point of the conventional IM is opened and is fed from both sides. The DC - bus voltage is Vdc/2 . CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Space phasor locations for Inverter-I (Left) and Inverter-II (Right)
6 (+-+) (-++) 4 1 (+--) 2 (++-) (-+-) 3 (--+) 5 7 (+++) (---) 8 (-++) 4’ 1’ (+--) 2’ (++-) (-+-) 3’ (--+) 5’ 6’ (+-+) 7’ (+++) (---) 8’ Vdc/2 CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

A total of 64 space phasor combinations are available
Voltage space phasor combinations from the dual inverter scheme A total of 64 space phasor combinations are available CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Dual Inverter fed induction motor with open end winding with isolated DC power supply a a’ Vdc/2 b b’ Vdc/2 c c’ IM with open-end winding Inverter - 1 Inverter - 2 Triplen harmonic suppression is achieved through the transformer isolation. CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

A new three-level inverter circuit topology cascading two two-level inverters CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

The power circuit configuration of a three-level inverter cascading conventional two two-level inverters CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Space vector locations of the proposed three-level inverter Similar to the conventional three-level inverter CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Salient features of the proposed three-level inverter configuration The power Bus structure is simple Can work as a conventional 2-level inverter in the lower voltage range The total VA rating of the the transformers is the same as that of the NPC configuration High voltage fast recovery diodes are not needed Three devices need to support the total DC bus voltage CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Experimental results: lower modulation range Pole Voltage waveforms of Inverter-1 (Top) and Inverter-2 (Bottom) Phase voltage Phase current at no-load |Vsr| = 0.4Vdc Vdc/2 = 150V A1 Vdc/2 = 150V A2 O CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Experimental results: higher modulation range Pole Voltage waveforms of Inverter-1 (Top) and Inverter-2 (Bottom) Phase voltage Phase current at no-load |Vsr| = 0.6Vdc CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Experimental results: over modulation range Pole Voltage waveforms of Inverter-1 (Top) and Inverter-2 (Bottom) Phase voltage |Vsr| = Vdc (Over-modulation) Phase current at no-load CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

A new five-level inverter circuit topology cascading two three-level inverters CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Introduction An inverter system for open-end winding induction motor is presented. Open-end winding IM is fed by two three-level inverters The 3-level inverters are realised by cascading two 2-level inverters This inverter scheme results in space phasor locations similar to a conventional Five-level Inverter CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

The schematic for the proposed five-level drive Vdc/4 Inverter A + S12 S16 S15 S13 S22 S26 S24 S5’ S23 S21 S25 INV 2 INV 1 S11 S14 - C1 C2 C4 S32 S36 S35 S33 S42 S46 S44 S43 S45 A4 B4 INV 4 INV 3 Inverter B S41 S34 S31 C3 B3 A3 IM O O’ A2 A1 B1 B2 Inverter A and Inverter B are 3-level inverters Each three level is formed by cascading two 2-level inverters INV1,INV2 Inverter A INV3,INV4 Inverter B CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

The 3-level inverter topology Vdc/4 Inverter A + S12 S16 S15 S13 S22 S26 S24 S5’ S23 S21 S25 INV 2 INV 1 S11 S14 - C1 C2 O A2 A1 B1 B2 VA2O Levels in A-leg 0 when S24 is on ( VA2O ) Vdc/4 when S21 and S14 on Vdc/2 when S21 and S11 on The 2-level inverters have DC-link of This 3-level structure does not require neutral point clamping diodes Vdc/4 CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Realization of five voltage levels across motor phases All legs of the three-level inverter can independently take any of the three levels when inverter-A and inverter-B are switched independently 5-levels can be generated across the winding. VA20 VA40’ VA2A4= VA20- VA40’ Vdc/4 Vdc/2 -Vdc/2 ( L1) -Vdc/4 ( L2) ( L3) Vdc/4 ( L4) Vdc/2 ( L5) * for the first three levels only Inverter-B is switching CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Space vector representation of the proposed Drive Similar to a five-level inverter 125 space vector combinations 96 sectors 61 locations Four layers CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

The Modulation scheme Multi-carrier PWM method is used Four triangular carriers 20% third harmonic added to the 3 reference signals A discreet DC shift is given to the reference signals depending on the speed range With this modulating scheme the inverter starts with 2-level operation and then moves to 3-level, 4-level and 5-level operation as speed increases CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Conventional SPWM For Low modulation index The reference wave set is placed at the middle of the carrier set Three levels are involved, therefore three-level waveform SPWM for the proposed Drive The reference wave set is placed at the middle of the lowermost carrier Only two levels are involved, therefore two-level waveform Only INV3 is switching ( the top 2-level inverter of Inverter-B) hence losses are only due to INV3 CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Conventional SPWM For next speed range (Vc /2< Vm <Vc ) Vc : Peak to peak amplitude of the carrier Vm : Peak amplitude of the reference wave SPWM for the proposed Drive The reference wave set is placed at the middle of the lower two carriers Three levels are involved, therefore three-level waveform Only INV4 and INV3 are switching (2-level inverters of Inverter-B) losses are only due to Inverter-B CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

For next speed range (Vc <Vm<3Vc/2 ) Conventional SPWM Five levels are involved, therefore five-level waveform All the 2-level inverters have to be switched SPWM for the proposed Drive The reference wave set is placed at the middle of second carrier ( C2) Four levels are involved, therefore four-level waveform Only INV2, INV4 and INV3 are switching INV1 is not switching CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

For the maximum speed range ( Vm> 3Vc/2 ) The reference set is at the center of the carrier set All the Five-levels are involved All the inverters have to be switched CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

2-Level operation Phase voltage shows 2-level waveform Motor phase voltage during 2-level operation Inverter-B,is switching between Vdc/2 and Vdc/ ( 200V and 100V) This is due to the switching of INV3 ( top inverter of Inverter-B). INV4 is clamped. Pole voltage of Inverter-B during 2-level operation Inverter-A is clamped to zero Pole voltage of Inverter-A during 2-level operation CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

3-Level operation Motor Phase Voltage shows 3-level waveform Inverter-B is switching as 3-level inverter (200V,100V,0V) Both the 2-level inverters of Inverter-B ( INV3 and INV4 are switching) Inverter-A still clamped to zero Motor phase voltage during 3-level operation Pole voltage of Inverter-B during 3-level operation CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

4-Level operation Motor Phase Voltage shows 4-level waveform Motor phase voltage during 4-level operation Inverter-B is switching as 3-level inverter (200V,100V,0V) Inverter-A is switching as 2-level inverter (100V,0V) This is due to the switching of INV2( bottom 2-level inverter ) Pole voltage of Inverter-B Pole voltage of Inverter-A CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

5-Level operation Motor Phase Voltage shows 5-level waveform Inverter-B is switching as 3-level inverter (200V,100V,0V) Motor phase voltage during 5-level operation Inverter-A is also switching as level inverter (200V,100V,0V) Pole voltages of Inverter-A (top) and Inverter B (bottom) [ experimental results] Pole voltages of Inverter-A and Inverter B Showing the phase relation (simulation results) CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Motor phase current 2-level operation 3-level operation 4-level operation 5-level operation CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Salient Features Feeding the open-end winding induction motor by 3-level inverters, results in voltage space phasors similar to a 5-level inverter The three level inverters used are realised by cascading Two 2-level inverters. This structure does not require neutral Clamping diodes . Compared with series connected H-bridge topology, the proposed drive scheme uses less number of power Supplies ( four against six required for H-bridge). CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Open end winding IM drive (Three level operation) with a single DC link CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Dual Inverter fed induction motor with open end winding with isolated DC power supply a a’ Vdc/2 b b’ Vdc/2 c c’ IM with open-end winding Inverter - 1 Inverter - 2 Triplen harmonic suppression is achieved through the transformer isolation. All the 64 - space phasor combinations can be used in this case. The transformers are bulky and expensive. CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Triplen harmonic contribution from various space- vector combinations (Twenty combinations are available with a triplen harmonic content of zero) CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Space phasor combinations with zero triplen harmonic contribution
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Proposed power circuit schematic (switched neutral)
+ Vdc - 3-ph Open-end winding IM Aux. Sw1 Aux. Sw2 Aux. Sw3 Aux. Sw4 Inv.1 Inv.2 C1 C2 Auxiliary switches SW 1 and SW 3 are opened when inverter-1 assume states 7 or 8.( switched neutral) Auxiliary switches SW 2 and SW 4 are opened when inverter-2 assume states 7’ or 8’. For “safe” combinations auxiliary switches are kept closed. CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Title Space phasor combinations used in the proposed control strategy Space phasor locations G,I,K,M,P,Q and R are forbidden. For combinations at H,J,L,N,Q and S the auxiliary switches need not be opened ( safe states). Other combinations have a zero state at one end. Appropriate auxiliary switches are opened to achieve triplen harmonic suppression CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Experimental results Pole voltages of individual inverters and the phase voltage (middle) with triplen content when |Vsr| = 0.4Vdc Actual motor phase voltage (left) and the motor phase current (right) when |Vsr| = 0.4Vdc CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

A Dual Two Level Inverter Scheme for an Open-end winding Induction Motor Drive with a Single DC Power Supply and improved DC bus Utilization CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

14 13 V1 V1 G H I K L M N S 18 17 16 15 V2 V2 8 The extreme vertices G, I, K, M, P and R are not switched. The DC-bus utilization is lower by about 15% Only 40 out of the 64 space vector combinations are used. P R CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Salient features of the switching strategy The triplen harmonic currents are denied a path by turning off the auxiliary switches. The auxiliary switch pairs toggle in this switching strategy with a fixed frequency. At a time only one inverter is connected to the DC link The DC-bus utilization is enhanced by about 15% compared to the earlier switching strategy. CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

(SW1,SW3) and (SW2, SW4) toggle at a fixed frequency CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Experimental results The motor phase voltage The motor phase current |Vsr| = 0.4Vdc CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Experimental results The triplen harmonic voltage in (vAO - vA’O’) Top trace: Voltage across the auxiliary switch Bottom trace: Current through the auxiliary switch |Vsr| = 0.4Vdc CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Experimental results: three-level operation
The motor phase voltage The motor phase current |Vsr| = 0.7Vdc The motor phase voltage with the earlier strategy when |vsr| = 0.6Vdc CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Experimental results: over modulation operation
The motor phase voltage The motor phase current |Vsr| = Vdc (Over-modulation) CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Experimental results The motor phase voltage The motor phase current The 12-step operation CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Multi-level structures with asymmetric DC link voltages

Asymmetrical DC-link voltages
A Multilevel Voltage Space vector Generation for an Open-end winding Induction Motor Drive using a dual-inverter scheme with Asymmetrical DC-link voltages CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Salient features of the proposed Drive A dual-inverter fed open-end winding IM drive is proposed, with asymmetric DC-link voltages (in the ratio 2:1). In this scheme, 64 space vector combinations are distributed over 37 space vector locations with 54 sectors. The switching ripple is lesser compared to the earlier scheme i.e. with equal DC-link voltages. The motor phase voltage waveform exhibits either 2-level waveform, 3-level waveform or the 4-level waveform depending upon the motor speed. CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Dual Inverter fed induction motor with open end winding with asymmetric voltages showing individual space phasor combinations a a’ 2/3Vdc b b’ 1/3Vdc c c’ IM with open-end winding Inverter - 1 Inverter - 2 ( ) 3 2 ( ++ - ) ( ) 3’ 2’ ( ++ - ) ( ) 4 1 (+- -) ( ) 4’ (+++) 7 8 (- - -) (+++) 7’ 8’ (- - -) 1’ (+- -) ( ) 5’ 6’ ( ) ( ) 5 6 ( ) 2 / 3 Vdc 1 / 3 Vdc CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Space phasor combinations for asymmetrical voltage dual - inverter drive 64 space vector combinations 54 sectors 37 locations three layers CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Experimental results Motor phase voltage (left) and the motor phase current (right) when |Vsr| = 0.2Vdc (2-level waveform) Normalized harmonic spectrum of the motor phase voltage illustrating the absence of the triplen -harmonic content for |Vsr| = 0.2Vdc CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Experimental results The actual motor phase voltage and motor phase current when |Vsr| = 0.5 Vdc (3-level waveform) Normalized harmonic spectrum of the motor phase voltage illustrating the absence of the triplen -harmonic content for |Vsr| = 0.5Vdc CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Experimental results Normalized harmonic spectrum of the motor phase voltage illustrating the absence of the triplen -harmonic content for |Vsr| = 0.8Vdc The actual motor phase voltage and motor phase current when |Vsr| = 0.8 Vdc (4-level waveform) CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Experimental results The actual motor phase voltage and motor phase current when |Vsr| = Vdc The harmonic spectrum of the motor phase voltage (showing the absence of the triplen harmonic content) for |Vsr| = Vdc CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Experimental results The actual motor phase voltage and motor phase current during square wave ( 18 - step operation) Normalized harmonic spectrum of the motor phase voltage illustrating the absence of the triplen -harmonic content for 18-step operation CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

A Multilevel Inverter System for an Open-end Winding Induction Motor

The salient features of the proposed scheme In the proposed scheme, a total of 512 voltage space vector combinations are present, distributed over 91 space vector locations. The three-level inverter in this scheme is realized by cascading two two-level inverters. In the lowest speed range, only one of the three inverters is switched. In the medium speed range two inverters are switched and in the higher speed range, all the three inverters are switched. This feature ensures that the switching losses are reduced in the lower and the middle range of speed. The motor phase voltage shows a 2-level waveform in the lowest speed range, a 3-level or a 4-level waveform in the medium speed range, a 5-level or a 6-level waveform in the higher speed range. This configuration needs three isolated power supplies. CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Schematic circuit diagram of the proposed inverter scheme vA2O vA3O’ vA2A3 = vA2O – vA3O’ 2/5Vdc 4/5Vdc 1/5Vdc -1/5Vdc 3/5Vdc CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Space vector locations from the individual inverter structures In the lower speed range, only inverter-3 is switched (2-level waveform) In the medium speed range Inverter-2 and Inverter-3 are switched (3-level or 4-level waveforms) In the higher speed range, all the inverters are switched. ( 5-level or 6-level waveform) CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Combined space vector locations (inner layers) Resultant space vector locations when inverter-1 is inactive i.e. clamped to the state 8(---) CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Combined space vector locations (outer layers) A total of 91 vector locations with 83 = 512 space vector combinations organized into 5 layers CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Title Motor phase voltage Motor phase current |Vsr| = 0.12 Vdc (Inner hexagon) Inverter-3 is alone switched CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Experimental results Motor phase voltage Motor phase current at no-load |Vsr| = 0.3Vdc (Layer-2) |Vsr| = 0.48Vdc (Layer-3) Inverter-1 and inverter-2 are switched in these two layers CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Experimental results Motor phase voltage Motor phase current at no-load |Vsr| = 0.65Vdc (Layer-4) Motor phase current at no-load Motor phase voltage |Vsr| = 0.83Vdc (Layer-5) All the three inverters are switched in these two layers CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Experimental results Motor phase voltage Motor phase current at no-load |Vsr| = Vdc (Over-modulation) 30 – step operation All the three inverters are switched in these two cases CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Seven-level voltage space phasor generation
scheme for an open-end winding induction motor drive with asymmetric dc link voltages CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Multi-level inverter configuration for induction motor with open-end winding structure with asymmetric DC Links + INV1 INV2 - INV3 INV4 Induction motor - - + + Higher-level voltage waveforms can be synthesized when individual inverters are supplied with unequal DC link voltages Seven-level space phasor generation from a five-level inverter DC link voltage of the top two-level inverters is Vdc/3 DC link voltage of the bottom two-level inverters is Vdc/6 CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Multi-level inverter configuration for induction motor with open-end winding structure with asymmetric DC Links + INV1 INV2 - INV3 INV4 Induction motor - - + + Requires only four isolated power supplies CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Seven-level inverter configuration with asymmetric dc link voltages
Vdc/2 Vdc/6 CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Seven-level voltage space phasor generation

Space vector diagram of seven-level inverter
combinations 127 space vector locations 216 triangular sectors CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Seven-level voltage space phasor generation scheme
Comparison: proposed inverter scheme with H-bridge inverter configurations Proposed seven-level inverter H-bridge seven-level inverter with symmetric DC links H-bridge inverter asymmetric DC links Maximum device rating Top inverter: Vdc/3 Bottom inverter: Top devices Vdc/6 Bottom devices Vdc/2 Vdc/6 Vdc/3 Switches 8 per phase 12 per phase DC link power supplies 2 (Vdc/3) 2 (Vdc/6) 9 (Vdc/3) 3 (2Vdc/3) 3 (Vdc/3) CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Space vector diagram of seven-level inverter
172 170 168 166 164 162 173 171 169 167 165 163 161 216 sectors 6 layers Over-modulation 174 114 112 110 108 106 160 175 115 113 111 109 107 105 159 176 116 68 66 64 62 104 158 177 117 69 67 65 63 61 103 157 178 118 70 34 32 30 60 102 156 179 119 71 35 33 31 29 59 101 155 180 120 72 36 12 10 28 58 100 154 181 121 73 37 13 11 9 27 57 99 153 182 122 74 38 14 2 8 26 56 98 152 183 123 75 39 15 3 1 7 25 55 97 151 184 124 76 40 16 4 6 24 54 96 150 216 185 125 77 41 17 5 23 53 95 149 215 186 126 78 42 18 20 22 52 94 148 214 187 127 79 43 19 21 51 93 147 213 188 128 81 44 46 48 50 92 146 212 189 129 81 45 47 49 91 145 211 A B C 190 130 82 84 86 88 90 144 210 191 131 83 85 87 89 143 29 In V/f mode, the length of the reference space vector is decided by the speed command. 192 132 134 136 138 140 142 208 193 133 135 137 139 141 207 194 196 1989 200 202 204 206 195 197 199 201 203 205 CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Phase-A voltage, phase-A current and common mode voltage waveforms for M.I.= 0.14 (Layer 1 operation) VA2A4 IA VOO’ CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Phase-A voltage, phase-A current and common mode voltage waveforms for M.I.= (Layer 2 operation) VA2A4 IA VOO’ CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Phase-A voltage, phase-A current and common mode voltage waveforms M.I.= (Layer 3 operation) VA2A4 IA VOO’ CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Phase-A voltage, phase-A current and common mode voltage waveforms for modulation index (Layer 4 operation) VA2A4 IA VOO’ CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Phase-A voltage and phase-A current waveforms for modulation index 0.94 (over- modulation operation) VA2A4 IA CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Phase-A voltage and phase-A current waveforms for 36-step mode VA2A4 IA CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Inverter operation under speed reversal:- Phase-A voltage and phase-A current VA2A4 IA CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

A High-Resolution Multi-Level Voltage Space Phasor Generation for an Open-end Winding Induction Motor Drive CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Introduction A topology for high resolution voltage space phasor generation for an open-end winding induction motor drive is presented The open-end winding induction motor is fed from both ends by two 3-level inverters with asymmetrical DC links This results in voltage space phasors equivalent to a conventional 9-level inverter The 3-level inverters used in the proposed drive, are realised by cascading two 2-level inverters CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

The power Circuit Inverter A Inverter B INV 1 INV 3 + - + 1/8Vdc S11 S13 S15 S35 S33 S31 3/8Vdc C1 A1 B1 C1 C3 B3 A3 C3 S32 S36 S34 Inverter A and Inverter B are 3-level inverters - S14 S16 S12 - + 1/8Vdc + S21 S23 S25 S45 S43 S41 C2 IM C4 C2 C4 B2 B4 3/8Vdc A2 A4 S24 S26 S22 S42 S46 S44 - INV 2 INV 4 O O’ Inverter A and Inverter B are formed by cascading 2-level inverters INV1,INV Inverter A ||| INV3,INV Inverter B INV1,INV /8Vdc INV1,INV /8Vdc CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

The levels across the machine phase winding Inverter A Levels in A-leg ( VA2O ) Inverter B Levels in A-leg ( VA4O’ ) Levels in A-phase of the machine ( VAA’= VA2O - VA4O’) 2/8 1/8 3/8 6/8 -2/8 L1 -1/8 L2 0 L3 1/8 L4 2/8 L5 3/8 L6 4/8 L7 5/8 L8 6/8 L9 CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Space vector representation 217 Locations 384 Sectors 9-levels in space vector Amplitudes along : 0,1/8, Vdc,2/8 Vdc, 3/8 Vdc ,4/8 Vdc , 5/8 Vdc , 6/8 Vdc , 7/8 Vdc and Vdc CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Conventional SPWM For Low modulation index The reference wave set is placed at the middle of the carrier set Three levels are involved, therefore three-level waveform SPWM for the proposed Drive The reference wave set is placed at the middle of the lowermost carrier Only two levels are involved, therefore two-level waveform Only INV3 is switching ( the top 2-level inverter of Inverter-B) hence losses are only due to INV3 CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

A progressive discreet DC shift in steps of Vc/2 is given to the reference wave set as the speed increases The inverter then moves through 3-level,4-level,5-level, 6-level,7-level,8-level and 9-level operation 9-level operation for the maximum speed range CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Experimental results : INV1 and INV2 DC-link : 150V ( 3/8 Vdc) INV3 and INV4 DC-link : 50V ( 1/8 Vdc) Layer 1 Phase voltage – 2-level waveform Only INV3 of Inverter-B is switching in 2-level mode ( 100 V and 50V) Pole voltage of Inverter-B CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Experimental results -Layer 2 Phase voltage – 3-level waveform Inverter-B in 3-level operation Inverter-A not switching ( 100V, 50V and 0V) CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Experimental results -Layer 3 Phase voltage – 4-level waveform Inverter-B in 3-level operation Inverter-A starts switching in 2-level mode ( 100V and 0V) CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Experimental results -Layer 6 Phase voltage – 7-level waveform Inverter-A in 2-level operation Inverter-B in 3-level mode CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Experimental results -Max speed range Phase voltage –9-level waveform Inverter-A also in 3-level operation ( 300V,150V,0V) Inverter-B in 3-level mode ( 100V,50V,0V) Inverter-A switching less frequently than Inverter-B CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

The Current waveforms During 8-level operation During 9-level operation The Harmonic Spectrum of the Phase Voltage During 9-level operation CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Common mode voltages and its effect on induction motor drive operation

Common-mode Voltage Generation by a Multi-level VSI
+ S11 S21 S31 C1 S12 S22 S32 o Vdc C B A a1 b1 c1 C2 S13 S23 S33 Induction Motor _ S14 S24 S34 N CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Three-level inverter configuration with common mode voltage elimination CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Common mode voltages and its effects PWM inverters generate high frequency, high amplitude common mode voltages, which induces ‘shaft voltage’ on the rotor side When the induced shaft voltage exceeds the breakdown voltage of the lubricant in the bearings, result in large bearing currents Problems associated: erosion of the bearing material, premature mechanical failure of bearings leading to motor failure, increase in total leakage current through the ground conductor resulting into increased conducted EMI and false tripping of relays PWM inverters which do not generate common mode voltage are suggested as a solution to the above problems CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Three-level inverter configuration with common mode voltage elimination CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

A dual two-level inverter scheme with common mode voltage elimination for an induction motor drive CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Schematic of dual inverter fed open end winding induction motor drive with isolated DC-links S41 A1 B1 C1 S12 S16 S14 S13 S11 S15 INV 1 + - Vdc/2 S22 S26 S24 S23 S25 INV 2 IM C2 B2 A2 O O’ CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

The voltage space vectors of the individual inverters B’ C B C’ 3 2’ 2 3’ D A D’ A’ 4 O 4’ O 1’ 1 5 E’ 6 F’ E F 5’ INV2 6’ INV1 Magnitude of space Phasors : CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

The voltage space vectors and space phasor combinations of the dual inverter 36’ K J I 25’ 35’ 26’ 37’ 27’ L 46’ 21’ 76’ 34’ 75’ 15’ C B H 45’ 86’ 85’ 16’ 31’ 38’ 28’ 24’ 41’ 47’ 77’ 17’ 14’ 71’ 81’ 18’ 74’ M D 11’, 33’ O 22’,44’ A G 48’ 56’ 87’,78’ 55’,66’ 74’ 65’ A -phase axis 32’ 88’ 23’ 42’ 82’ 73’ 13’ 72’ 43’ 67’ 54’ N E F S 51’ 57’ 61’ 68’ 12’ 64’ 58’ 83’ 62’ 53’ 52’ P R Q 63’ CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Voltage space vector combinations producing zero common mode voltage in the motor phase windings CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Schematic of dual inverter fed open end winding induction motor drive with single DC-links S41 A1 B1 C1 S12 S16 S14 S13 S11 S15 INV 1 + - Vdc/2 S22 S26 S24 S23 S25 INV 2 IM C2 B2 A2 O CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Voltage vectors without triplen contribution J K I 35’ 26’ L 46’ 2 H 3 15’ 31’ 24’ 33’ 22’ M 4 O 1 G 44’ 11’ A -phase axis 55’ 66’ 77’ 88’ 42’ 13’ N 51’ 64’ S 5 6 62’ 53’ P R Q CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

The space phasor combinations for active vectors and zero vectors used in the present work (for sequence-1) 35’ J K I 31’ L 2 H 15’ 3 33’ 55’ M 11’ O 11’ 1 4 G 55’ 33’ A -phase axis 51’ N S 5 6 13’ P R Q 53’ CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

The reference space phasor Vsr for the dual inverter 35’ J K I 31’ L 2 H 15’ 3 33’ 55’ M G 4 11’ O 11’ 1 55’ 33’ A -phase axis 5 51’ N S 6 13’ P R Q 53’ CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Experimental results : lower speed range Pole voltage and its FFT Phase voltage and its FFT CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Experimental results : higher speed range Pole voltage and its FFT Phase voltage and its FFT CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Three-level inverter configuration with common mode voltage elimination for an induction motor drive CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Three-level inverter configuration with common mode voltage elimination A three – level inverter scheme based on open-end winding configuration is proposed, which, uses only half the DC link voltage, compared to the scheme based on conventional NPC inverter The proposed scheme generates the three-level voltage waveforms across the motor phases with Zero common mode voltage in the motor phase voltage Zero common mode voltage in the pole voltage CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

The five-level inverter configuration CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

space vector combinations for inverter-A , inverter-B
B axis -+- 0+- ++- K J I H G B C A F E D L M N O P Q R -0- 0+0 -+0 00- ++0 +0- +++ 000 --- A axis -00 0++ 0-- +00 -++ +-- --0 00+ 0-0 +0+ -0+ +-0 --+ 0-+ +-+ C axis Vdc /2 CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Five-level Inverter voltage space vector representation B-phase Axis 46 45 44 43 42 Shaded inverter voltage space phasor locations produce zero common mode voltage in the phase voltage of IM 68 66 64 62 69 67 65 63 61 47 26 25 24 23 41 70 34 32 30 60 71 35 33 31 29 59 48 12 11 22 27 10 40 72 36 28 12 10 58 73 27 37 13 11 9 57 49 28 13 4 3 9 21 39 74 26 38 14 2 8 56 39 7 25 75 15 3 1 55 29 1 50 14 5 2 8 20 38 76 40 16 6 24 54 96 4 23 77 41 17 5 53 95 51 30 15 6 7 19 37 61 A-phase Axis 78 42 20 22 52 94 18 51 79 43 19 21 93 52 31 16 17 18 36 60 81 44 46 48 50 92 81 45 47 49 91 32 33 34 35 59 53 82 84 86 88 90 83 85 87 89 54 55 56 57 58 C-phase Axis Vdc CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Inverter voltage space phasor locations with zero common mode voltage in the phase voltage of IM B-phase Axis I’ J’ H’ K’ B’ G’ C’ A’ A- phase axis L’ R’ D’ F’ M’ E’ Q’ N’ P’ O’ Vdc C-phase Axis CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Three-level inverter configuration with common mode voltage elimination Classification of inverter voltage vectors of three-level inverters CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Voltage space vectors of inverter-A (belonging to group C, D and E) in a three dimensional plane: α-β-0 plane Vcm1 ++- -++ +-+ +00 0+0 00+ Group C 0+- +0- -+0 -0+ 0-+ +-0 000 Group D -+- +-- --+ 00- Group E -00   Vcm 0-0 CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

The resultant three-level space vector configuration when group D switching states are used to switch inverters-A and inverter-B CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Inverter configuration with common mode voltage elimination

Three-level inverter configuration with common mode voltage elimination Salient Features A three-level inverter configuration with common mode elimination is proposed for an induction motor drive with open-end windings. Common mode voltage generated across the motor phases is zero. Suppresses the common mode currents which otherwise will flow in the machine windings. Common mode voltage in the inverter pole voltage is zero. The problems associated with the common mode voltages inducing currents in the leakage capacitances are completely eliminated (as the electrostatic coupling between stator winding to stator iron and between stator winding and rotor iron is ineffective) Only two power supplies are required whereas the equivalent three-level inverter configuration with common mode elimination based on H-bridge topology requires six isolated power supplies. DC link voltage requirement is only half to that of the conventional three-level inverter configuration with common mode elimination. CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Output vectors selected for inverter switching +0- , 000 000 , 0-+ -+0 , 000 000 , +0- 0-+ , 000 000, -+0 0+- , -0+ -0+, +-0 +-0 , 0+- +0- , -0+ 0+- , 0-+ -+0 , +-0 -0+ , +0- +-0,-0+ 0+-,+-0 -0+ , 0+- +-0 , -+0 0-+ , 0+- 000, 000 B-phase Axis A –phase axis 1 Vdc C-phase Axis CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Pole voltage waveforms for modulation index 0.4 (Layer 1 operation) and its FFT CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Phase-A voltage and phase-A current waveform for modulation index 0.4 and FFT of phase voltage (Layer 1) CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Pole voltage waveforms for modulation index 0.7 (Layer 2 operation) and its FFT CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Phase-A voltage and phase-A current waveform for modulation index 0.7 and FFT of phase voltage (Layer 2) CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Pole voltage waveforms for modulation index 0.95 (over-modulation operation) and its FFT CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Phase-A voltage and phase-A current waveform for modulation index 0.95 and FFT of phase voltage CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Pole voltage waveforms for twelve-step mode and its FFT CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Phase-A voltage and phase-A current waveform for twelve-step mode and FFT of phase voltage CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Five-level inverter configuration with common mode voltage elimination for an induction motor drive CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Power Scheme of One Leg of Proposed Five-level Inverter by Cascading Conventional Two-level and Three-level VSIs IGBT Gating Logic Level Pole Voltage State of the switch* S11 S21 S24 S41 2 Vdc/4 1 Vdc/8 -1 -Vdc/8 -2 -Vdc/4 *[“1”  ON, “0”  OFF] S11-S14, S21-S34, S24-S31, and S41-S44 are complementary pairs of switches CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Power Schematic for The Nine-level Inverter Configuration

Switching States and Voltage Space Vector Locations of Inverter-A (a Five-level Inverter) 96 Sectors 61 Vectors 125 Switching States CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Groups of Common-mode Voltage Generated by Individual Five-level Inverter
Switching state of five-level inverter VCM 1 222 Vdc/4 2 122, 212, 221 5Vdc/24 3 022, 112, 121, 202, 211, 220 Vdc/6 4 012, 021, 102, 111, 120, 201, 210, 22-1, 2-12, -122 Vdc/8 5 002, 011, 020, 101, 110, 12-1, 1-12, 200, 21-1, 22-2, 2-11, 2-22, -112, , -222 Vdc/12 6 001, 010, 02-1, 0-12, 100, 11-1, 12-2, 1-11, 1-22, 20-1, 21-2, 2-10, , -102, -111, -120, -212, -221 Vdc/24 7 000, 01-1, 02-2, 0-11, 0-22, 10-1, 11-2, 1-10, 1-21, 20-2, 2-1-1, 2-20, , -110, -12-1, -1-12, -202, -211, -220 8 00-1, 01-2, 0-10, 0-21, 10-2, 1-1-1, 1-20, 2-1-2, 2-2-1, -100, -11-1, , -1-11, -1-22, -201, -210, -22-1, -2-12 -Vdc/24 9 00-2, 0-1-1, 0-20, 1-1-2, 1-2-1, 2-2-2, -10-1, -11-2, -1-10, -1-21, -200, , -22-2, -2-11, -2-22, -Vdc/12 10 0-1-2, 0-2-1, 1-2-2, -10-2, , -1-20, -20-1, -21-2, -2-10, -2-21 -Vdc/8 11 0-2-2, , , -20-2, , -2-20 -Vdc/6 12 -1-2-2, , -5Vdc/24 13 -2-2-2 -Vdc/4 CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Groups of Switching States and Amplitude of Resulting Common-mode Voltage in Five-level Inverter (Inverter-A and Inverter-A’) CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Voltage Vector With Corresponding Switching State Resulting Zero Common-mode Voltage in Five-level Inverter (Inv.-A and Inv.-A’) 24 Sectors 19 Vectors 19 Switching States CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Combined Voltage Space Vector Locations of a Dual Five-level Inverter Fed Open-end Winding IM Drive (a Nine-level Inverter) 384 Sectors 217 Vectors 15,625 Switching States CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Number of Redundant Switching States Available for Voltage Vectors of Five-level Inverter with Zero Common-mode Voltage 96 Sectors 61 Vectors 361 Switching States CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Switching State Combination Selected to Generate The Voltage Space Phasors of Five-level Inverter With Zero CMV 96 Sectors 61 Vectors 61 Switching States CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Power Scheme of Proposed Five-level Inverter With CME

Phase voltage spectrum
Experimental results Two-level operation m=0.2 Pole voltage spectrum Phase voltage spectrum

Experimental results Three-level operation m=0.33 Pole voltage spectrum Phase voltage spectrum

Experimental results Four-level operation m=0.6 Pole voltage spectrum Phase voltage spectrum

Experimental results Five-level operation m=0.72 Pole voltage spectrum Phase voltage spectrum

Experimental results Over modulation m=0.97 Pole voltage spectrum Phase voltage spectrum

Five-level operation m= 0.72
Experimental results Four-level operation m=0.6 Five-level operation m= 0.72 Over modulation m = 0.97

Three-level inverter scheme with common mode
voltage elimination and dc-link capacitor voltage balancing for an open end winding induction motor drive CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Power schematic of a three-level inverter with common-mode voltage elimination Each side on motor is fed with three-level inverters Requires half the DC link voltage, compared to the scheme based on conventional NPC inverter The proposed scheme generates the three-level voltage waveforms across the motor phases with Zero common mode voltage in the motor phase voltage Zero common mode voltage in the pole voltage CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Three-level inverter with common-mode voltage elimination Salient Features Multiplicity of inverter vector locations has been effectively utilized to arrive at a DC Link capacitor voltage-balancing scheme The proposed capacitor voltage-balancing scheme is implemented without compromising on the SVPWM scheme and a simple hysteresis controller can be used to balance the DC link capacitor voltages Requires only one isolated passive front-end power supply CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

The switching combinations for three-level inverter with common mode voltage elimination Proposed scheme generates the three-level voltage waveforms across the motor phases with Zero common mode voltage in the motor phase voltage Zero common mode voltage in the pole voltage The DC Link voltage is half as compared to the three-level NPC inverter Switching combination ‘+0-, -0+’ means inverter-A state is ‘+0-‘ inverter-B state is ‘-0+’ CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Inverter-induction motor system model Each leg of individual three-level inverter is modeled as a three pole switch 1 => - Vdc/2 2 => 0 3 => + Vdc/2 Switching function ‘S’ = if switch is connected to -Vdc/2 2 if switch is connected to – 0 3 if switch is connected to Vdc/2 CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Inverter-induction motor system model Source current – iS Currents drawn from DC link- i1, i2, i3 Inverter-A currents -i1A,i2A,i3A, Inverter-A currents -i1B,i2B,i3B Induction motor currents- ia, ib, ic CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Analysis of DC link capacitor voltage unbalance for proposed three-level inverter configuration The inverter pole voltages with respect to negative DC rail, in terms of capacitor voltages CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Analysis of DC link capacitor voltage unbalance for proposed three-level inverter configuration The currents drawn from the DC Link nodes (i1,i2,i3) in terms of motor currents (ia, ib, ic) Inverter-A: Inverter-B: Motor currents Motor currents CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Analysis of DC link capacitor voltage unbalance for proposed three-level inverter configuration The current drawn from the middle point on the DC link is responsible for unbalance CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Classification of the inverter voltage vectors 1 SV MV LV ZV Classification is based on Voltage produced in the output Connection of IM phase winding to the Capacitors LV: Large Voltage Vectors ZV: Zero Voltage Vectors SV: Small Voltage vectors MV: Medium Voltage vectors CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Large Voltage Vectors (LV) and their effect on DC link capacitor voltages Two windings directly across full DC link One winding short circuited at middle DC link point No effect on capacitor voltages as load current is drawn directly from source C2 B A C C1 G’ (+0-, -0+) CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Middle Voltage Vectors (MV) and their effect on DC link capacitor voltages One winding directly across full DC link One windings across each capacitor The difference between these two winding currents is drawn through the mid-point of DC link Has unbalancing effect on capacitor voltages C2 C2 B A C C C1 A C1 B 0+- , -0+ +0- , 0-+ (a) (b) Each MV vector location has two switching combinations The IM phase windings are connected to opposite capacitors in these two combinations Ex: vector location H’ (a) 0+-,-0+ A phase bottom capacitor and B phase top capacitor (b) 0+-,-0+ A phase top capacitor and B phase bottom capacitor CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Space vector combinations and their effect on DC link capacitor voltages inverter vector location A’ (Small Voltage vector) C2 C1 (b) +0-, 000 C A B C2 C1 One winding across each capacitor One winding across each capacitor B C A NSV NSV (a) 000,-0+ Normal Small Voltage Vector Normal Small Voltage Vector C2 C1 (c) +-0 , 0-+ A C B Two windings across TOP capacitor C2 C1 (d) 0+- , -+0 A C B Two windings across BOTTOM capacitor USV LSV Upper Small Voltage Vector Lower Small Voltage Vector CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Summary: Classification of switching combinations of proposed inverter voltage vector locations +-0 , 0-+ 000 , -0+ +0- , 000 0+- , -+0 -+0 , -0+ 0+- , 000 000 , 0-+ +0- , +-0 0+- , +0- 000 , +-0 -+0 , 000 -0+ , 0-+ 0-+ , +-0 -0+ , 000 000 , +0- -+0 , 0+- -0+ , -+0 000 , 0+- 0-+ , 000 +-0 , +0- +0- , 0+- +-0 , 000 000,-+0 0-+ , -0+ 0+- , -0+ +0- , 0-+ -0+, +-0 -+0 , +0- +-0 , 0+- 0-+ , -+0 +0- , -0+ 0+- , 0-+ -+0 , +-0 -0+ , +0- +-0,-0+ +0-,-+0 -+0 , 0-+ 0+-,+-0 -0+ , 0+- 0-+ , +0- +-0 , -+0 0-+ , 0+- LV: Large Voltage Vectors ZV: Zero Voltage Vectors MV: Medium Voltage vectors USV: Upper Small Voltage vectors NSV: Normal Small Voltage vectors LSV: Lower Small Voltage vectors CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

DC link capacitor voltage balancing scheme for the proposed three-level inverter fed induction motor drive 000 , -0+ +0- , 000 0+- , 000 000 , 0-+ 000 , +-0 -+0 , 000 -0+ , 000 000 , +0- 000 , 0+- 0-+ , 000 +-0 , 000 000,-+0 0+- , -0+ +0- , 0-+ -0+, +-0 -+0 , +0- +-0 , 0+- 0-+ , -+0 +0- , -0+ 0+- , 0-+ -+0 , +-0 -0+ , +0- +-0,-0+ +0-,-+0 -+0 , 0-+ 0+-,+-0 -0+ , 0+- 0-+ , +0- +-0 , -+0 0-+ , 0+- ZV and LV do not have any unbalancing effect on the DC link capacitor voltages MV and NSV group generate very low voltage unbalance. Each have two switching combinations with phase windings EXCHANGING their connections to DC link capacitors. Thus, effect of one switching combination on the capacitor voltages is nullified by another switching combination Alternate switching of NSV and MV switching combinations in consecutive sampling durations will maintain the capacitor voltages balanced. Thus inverter voltage vectors belonging to ZV, NSV, MV and LV can be used effectively to maintain the voltage balance across the DC Link capacitors No voltage/current feedback required Works on alternate switching of NSV and MV switching combinations CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

The sequence of various switching combinations during POS_SEQ and NEG_SEQ POS_SEQ NEG_SEQ A’ G’ R’ +0-, -+0 000, -0+ +0-, 000 +0-, -0+ TS 2*TS +-0, -0+ (a) Sector formed by inverter vectors A’-G’-R’ B’ 0+- , 000 000, 000 000,000 000, 0-+ (b) Sector formed by inverter vectors 0-A’-B’ (c) SEQ signal TS TS high low CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Sector formed by inverter voltage vectors A’-G’-R’ I’ Alternate switching combinations are selected for A’ (NSV) and R’(MV) inverter voltage vectors in the consecutive sampling interval The capacitor voltage unbalance in sampling interval POS_SEQ is nullified in next sampling interval NEG_SEQ J’ H’ K’ B’ G’ C’ A’ Y’ 0’ R’ L’ D’ F’ M’ E’ Q’ Q’ N’ P’ O’ A’ G’ R’ A’ A’ R’ G’ A’ 000, -0+ +0-, -0+ +-0, -0+ 000, -0+ +0-, 000 +0-, -+0 +0-, -0+ +0-, 000 TS TS high POS_SEQ NEG_SEQ low 2*TS TS CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Sector formed by inverter voltage vectors 0-A’-B’ I’ Alternate switching combinations are selected for A’ (NSV) and B’(NSV) inverter voltage vectors in the consecutive sampling interval The capacitor voltage unbalance in sampling interval POS_SEQ is nullified in next sampling interval NEG_SEQ J’ H’ K’ B’ G’ Y’ C’ A’ 0’ R’ L’ D’ F’ M’ E’ Q’ Q’ N’ P’ O’ A’ B’ B’ A’ 000, 000 000, -0+ 000, 0-+ 000, 000 000, 000 0+- , 000 +0-, 000 000,000 TS TS high POS_SEQ NEG_SEQ low 2*TS TS CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Open loop DC Link capacitor voltage balancing scheme SVPWM modulator SEQ Switching Combination Selector Gate signal decoding Gate signals State DSP PAL CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Open loop DC Link capacitor voltage balancing controller (Simulation results) DC Link Voltage Capacitor voltages CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Deviation in the capacitor voltages when the open loop DC Link balancing controller is turned off (Simulation results). DC Link Voltage Capacitor voltages CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Harmonic frequency distribution of phase voltages for balanced and unbalanced capacitor voltage conditions Low order even harmonics causes damaging effects to the machine because of the current harmonics resulting in torque pulsations and increased machine losses CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Open loop DC Link capacitor voltage balancing scheme Disadvantage: Gradual drift in the capacitor voltages in the open loop scheme Possible Reasons: Use of the asynchronous PWM, Unequal time durations of the MV and NSV inverter vectors in consecutive switching intervals Unbalanced load currents etc sec CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Hysteresis controller based closed loop DC Link balancing scheme Switching combinations from USV charge lower capacitor and discharge upper capacitor Switching combinations from LSV discharge lower capacitor and charge upper capacitor USV and LSV group switching combinations are used to balance the capacitor voltages Hysteresis Controller vC2 vC1 Control Band vC Hysteresis controller selects the LSV or USV group instead of NSV depending upon the difference in the capacitor voltages, vC Closed loop scheme involves sensing the capacitor voltages CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Hysteresis controller based closed loop DC Link balancing scheme Inverter Switching Vector Location Combination Selector gate signals decoding Hysteresis Controller SEQ State vC2 vC1 DSP PWM Algorithm A B Induction motor PAL CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Operation of closed loop controller for DC link balancing (Simulation results) Capacitor voltages vC Controller output ‘state’ CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

The deviation in the capacitor voltages when the DC Link voltage-balancing scheme is turned off for a small interval CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

DC Link voltage-balancing scheme in 12-step mode SV are not switched for longer duration in the 12-step mode Capacitor voltages deviate from the balanced state CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

DC Link voltage-balancing scheme in 12-step mode Slight reduction in the modulation index restores the capacitor voltages to balanced state in 12-step mode CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Experimental Results CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Balancing of DC link capacitor voltages VC1 and VC2 during steady state operation VC1, VC2 CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Balancing of the DC Link capacitor voltages after the controller is disabled for small interval, inner layer operation VC1 VC2 CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Balancing of the DC Link capacitor voltages after the controller is disabled for small interval, outer layer operation VC1 VC2 CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

The DC link voltages and machine phase current under while machine operating in inner layer is accelerated to outer-layer and then to over-modulation Phase current VC1, VC2 CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

The DC link voltages and machine phase current under while machine operating in inner layer is subjected to speed reversal Phase current VC1, VC2 CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Space vector PWM signal generation for multi-level inverters using only the sampled amplitudes of reference phase voltages CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Space vector PWM signal generation for multi-level inverters
using only the sampled amplitudes of reference phase voltages Conventional Space Vector Based PWM Identify the sector Determine the timings Determine the Actual vectors Generate the Gate signals Sector Identification a. With Angle and magnitude information b. Using level comparators Timing a. Direct equations b. Mapping the sector to an appropriate inner sector CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Space vector PWM signal generation for multi-level inverters
using only the sampled amplitudes of reference phase voltages In the Proposed Work Sector identification is not required No need to compute switching times for each vector Does not use look-up tables to select vectors The inverter leg switching times are directly obtained with a simple algorithm using only the sampled amplitudes of the reference phase voltages Faster computations Generate the inverter gate signals for the entire modulation range extending up to six step mode CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Two level SVPWM CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Offset voltage determination for Two level SVPWM Addition of Voffset1 centers the active inverter vectors in the switching interval for two-level inverters but not for multilevel inverters The max phase may not determine the third cross, min phase may not determine the first cross Correct determination of the phases which determines the first -cross,second-cross and third-cross is required for multilevel inverters CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Reference voltages and triangular carriers for a five-level SPWM CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA

Power Converters and Drives Lab -a Research Overview

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Power Converters and Drives Lab -a Research Overview

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Presentation on theme: "Power Converters and Drives Lab -a Research Overview"— Presentation transcript:

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