1. Multivibrator Circuits
Bistable Multivibrator (Flip-Flops)
Astable Multivibrator (Clocks or Oscillators)
Schmitt-Trigger Inverter (7414)
555 Timer
Crystal Oscillator
Monostable Multivibrator (One-Shots)
Non-Retriggerable (74121)
Retriggerable (74123)
VHDL Coding
It is assumed that you understand the operation of FFs (D-type and J-K) from your prior digital courses. See Fundamentals of Digital Logic, sections 7.1 through 7.7, to review this material.
FFs have two stable states, so are considered bistable multivibrators.
Astable or free-running multivibrators switch back and forth between two unstable states. This makes it useful for generating clock signals for synchronous circuits.
Crystal control may be used if a very stable clock is needed. Crystal control is used in microprocessor based systems and microcomputers where accurate timing intervals are essential.
One shots (OS) have one stable state and are considered monostable multivibrators. OS produce a pulse of a predefined width every time the trigger input is activated.
ECE M. A. Jupina, VU, 2014

2. Some Key Lecture Objectives
To learn how timing signals are generated at low frequencies (< 1 MHz) and high frequencies (>1 MHz).
To learn how clock and pulse signals are generated either through the use of ICs or VHDL coding.
To gain a better understanding of how to apply timing signals in a digital design.
ECE M. A. Jupina, VU, 2014

3. Schmitt-Trigger Inverter
Note the hysteresis symbol on the Schmitt Trigger Inverter
Accepts slow changing signals and produces a signal that transitions quickly.
A Schmitt trigger device will not respond to an input until it exceeds the positive or negative going threshold.
There is a separation between the two threshold levels. This means that the device will “remember” the last threshold exceeded until the input goes to the opposite threshold.
(a) If input transition times are too long, a standard logic device-output might oscillate or change erratically; (b) a logic device with a Schmitt-trigger type of input will produce clean, fast output transitions.
ECE M. A. Jupina, VU, 2014

4. Schmitt-Trigger Inverter Operation
VOH
VOL
VTL
VTH
VOUT
VIN
As VIN increases, VOUT = VOH until VIN > VTH
then VOUT = VOL
When VIN begins to decrease, VOUT = VOL until VIN < VTL
then VOUT = VOH
Hysteresis graph is shown.
ECE M. A. Jupina, VU, 2014

5. Schmitt-Trigger Oscillator
IIN
Manufacturers’ equations are given (assumption is that the input current is not zero).
ECE M. A. Jupina, VU, 2014

6. Analysis of a Schmitt-Trigger Oscillator
VC(t)
VTH
VTL t
VOH
VOUT(t)
VOL TL TH
t = t = 0'
Assume Iin = 0, thus IR(t) = IC(t)
In this analysis we will assume that the input current is zero in order to calculate fosc.
Capacitor Discharging
Capacitor Charging
VC(t)
VC(t)
VOL
VOH
ECE M. A. Jupina, VU, 2014

7. Analysis of a Schmitt-Trigger Oscillator Continued
Capacitor Discharging
Capacitor Charging
Since TH < TL the duty cycle is less than 50%.
ECE M. A. Jupina, VU, 2014

8. Example: Show how to use a 74LS14 Schmitt-trigger inverter to produce an approximate square wave with a frequency of 10 KHz.
Solution:
ECE M. A. Jupina, VU, 2014

9. PSPICE Simulation of a Schmitt-Trigger Oscillator (7414)
TTL 7414 Hex Inverter – unused inputs on the IC are tied to ground to reduce noise in the circuit.
Analog output signal and the voltage signal across the capacitor is shown on the bottom.
Digital output signal representation is shown on the top.
VTH=1.7V and VTL=0.9V.
VOH=3V and VOL=0.1V.
For simulation purposes, the initial condition on the input is set to zero volts (IC=0).
ECE M. A. Jupina, VU, 2014

10. 555 Timer as an Astable Multivibrator
1 – Ground 5 – FM Input (Tie to gnd via bypass cap)
2 – Trigger 6 – Threshold
3 – Output 7 – Discharge
4 – Reset (Set HIGH for normal operation) 8 – Voltage Supply (+5 to +15 V)
ECE M. A. Jupina, VU, 2014

11. Block Diagram of a 555 Timer Configured as an Oscillator
ECE M. A. Jupina, VU, 2014

12. 555 Timer Block Diagram Contents
Resistive voltage divider (equal resistors) sets threshold voltages for comparators
V1 = VTH = 2/3 VCC V2 = VTL = 1/3 VCC
Two Voltage Comparators
For A1, if V+ > VTH then R =HIGH
For A2, if V- < VTL then S = HIGH
RS FF
If S = HIGH, then FF is SET, = LOW, Q1 OFF, VOUT = HIGH
If R = HIGH, then FF is RESET, = HIGH, Q1 ON, VOUT = LOW
Transistor Q1 is used as a Switch
ECE M. A. Jupina, VU, 2014

13. Timing Diagram of a 555 Oscillator
VC(t)
VTH
VTL t
VCC
VOUT(t) TL TH t
t = 0 t = 0'
ECE M. A. Jupina, VU, 2014

14. Operation of a 555 Oscillator
Assume initially that the capacitor is discharged.
For A1, V+ = VC = 0V and for A2, V- = VC = 0V, so R=LOW, S=HIGH, = LOW , Q1 OFF, VOUT = VCC
Now as the capacitor charges through RA & RB, eventually VC > VTL so R=LOW & S=LOW.
FF does not change state.
RA RB
VC(t)
VCC
ECE M. A. Jupina, VU, 2014

15. Operation of a 555 Oscillator Continued
Once VC  VTH
R=HIGH, S=LOW, = HIGH ,Q1 ON, VOUT = 0
Capacitor is now discharging through RB and Q1 to ground.
Meanwhile at FF, R=LOW & S=LOW since
VC < VTH. RB
VC(t) Q1
ECE M. A. Jupina, VU, 2014

16. Operation of a 555 Oscillator Continued
Once VC < VTL
R=LOW, S=HIGH, = LOW , Q1 OFF, VOUT = VCC
Capacitor is now charging through RA & RB again.
RA RB
VC(t)
VCC
ECE M. A. Jupina, VU, 2014

17. Analysis of a 555 Oscillator
Capacitor Discharging
Capacitor Charging
ECE M. A. Jupina, VU, 2014

18. Examples Example: Design a 555 Oscillator to produce an approximate
square-wave at 40 KHz. Let C > 470 pF.
Examples
One Possible
Solution:
F=40KHz; T=25µs; t1=t2=12.5µs
For a square-wave RA<<RB; Let RA=1K and RB=10K
t1=0.693(RB)(C); 12.5µs=0.693(10K)(C); C=1800pF
T=0.693(RA+2RB)C: T=0.693(1K+20K)1800pF
T=26.2µs; F=1/T; F=38KHz (almost square-wave).
Example: A 555 oscillator can be combined with a J-K FF to produce a 50% duty-cycle signal. Modify the above circuit to achieve a 50% duty-cycle, 40 KHz signal.
One Possible
Solution:
Reduce by half the 1800pF. This will create a T=13.1µs or F=76.35 KHz
(almost square-wave). Now, take the output of the 555 Timer and connect
it to the CLK input of a J-K FF wired in the toggle mode (J and K inputs
connected to +5V). The result at the Q output of the J-K FF is a perfect
38.17 KHz square-wave.
ECE M. A. Jupina, VU, 2014

19. Problem 10.24 - The 555 Programmable Timer Chip
5 V 4 8 R a
Clock 3 7
(output)
555 R
Timer b 2 6 C 1 1 5
Problem from your textbook.
Note for part (a): the 100 pF is generally too small since C1 should be at least a 470 pF capacitor or larger. However, in order to get a ~50% duty cycle, ~500 KHz waveform with Ra at least 1 K ohm, then C1 must be less than 500 pF.
0.01 m F
(a) For 50% duty cycle and 500 KHz frequency, C1 = 100 pF, then Ra = 1 kΩ and Rb = 14 kΩ
(b) For 75% duty cycle and 500 KHz frequency, C1 = 1000 pF, then Ra = 1.42 kΩ and Rb = 0.71 kΩ
ECE M. A. Jupina, VU, 2014

20. PSPICE Simulation of a 555 Oscillator
R1=R2, duty cycle = 66% and f =16 KHz
ECE M. A. Jupina, VU, 2014

21. Crystal Oscillator
An oscillator circuit that uses a piezoelectric crystal.
Piezoelectric materials support an exchange of energy between mechanical compression and applied electric field.
If a potential is applied between the electrodes, forces will be exerted on the bound charges within the crystal. Deformations take place within the crystal and an electromechanical system is formed which will vibrate when properly excited.
Mechanical deformation along one crystal axis will produce an electric potential along another axis. Conversely, an applied voltage will deform the crystal. If the applied voltage is sinusoidal with a variable frequency, a crystal will go into mechanical oscillation and exhibit a number of resonance frequencies. Near a resonance an oscillating crystal has the terminal characteristics of an LC network with an extremely high Q.
ECE M. A. Jupina, VU, 2014

22. Crystal Oscillator, Continued
The oscillation frequency (10 KHz – 80 MHz) is very precisely determined by the physical dimensions of the crystal.
High Q (1000 – 10,000) resonators are usually built using quartz single crystal or ceramic materials.
These resonators are extremely stable (ppm’s) with respect to time and temperature.
To generate clock frequencies into the GHz range, DPLL (Digital Phase Lock Loops) are used for frequency multiplication. fo
XTAL
OSC
DPLL
N•fo
ECE M. A. Jupina, VU, 2014

23. Crystal Oscillator Circuit Example
crystal oscillator symbol
and equivalent circuit
Pierce oscillator circuit
The crystal is placed in the feedback loop of the circuit between the input (gate electrode) and output (drain electrode) to make the FET circuit unstable and thus oscillate.
Yi – input admittance of the osc circuit – made-up of RG, CG, and CGS of the transistor
YN =I/VGS – admittance of the rest of the osc circuit
Oscillation occurs at the frequency where Yi + YN = 0
equivalent circuit of Pierce oscillator
ECE M. A. Jupina, VU, 2014

24. Example: 50 MHz Oscillator on the Altera DE2 Board
ECE M. A. Jupina, VU, 2014

25. Clock Divider
Use a clock divider (written in VHDL) to produce clock signals of lower frequencies.
Divide 50 MHz down to 1 MHz, 100 KHz, etc
All clock signals of different frequencies come from the same source. Very useful since all clock signals will be in phase with one another.
ECE M. A. Jupina, VU, 2014

26. Non-Retriggerable One-Shot (OS)
Changes from stable state to quasi-stable state for a period of time determined by external components (usually resistors and capacitors).
One shots are called monostable multivibrators because they have only one stable state.
A nonretriggerable OS will trigger once and then ignore the trigger input as long as the output pulse is still active (i.e., Q=1 and Qnot =0).
They are prone to triggering by noise so, tend to be used in simple timing applications.
ECE M. A. Jupina, VU, 2014

27. Comparison of Non-Retriggerable and Retriggerable OS responses for tPULSE = 2 ms
A nonretriggerable OS will trigger once and then ignore the trigger input as long as the output pulse is still active (i.e., Q=1 and Qnot =0).
A retriggerable OS starts an output pulse in response to a trigger and then restarts the internal pulse timer every time a subsequent trigger edge occurs before the output pulse is complete.
ECE M. A. Jupina, VU, 2014

28. Example Example: Refer to the waveforms in (a) on previous page.
Change the OS pulse duration to 0.5 ms and determine the Q output for both types of OS. Then repeat using a pulse duration of 1.5 ms.
Example
Solution:
ECE M. A. Jupina, VU, 2014

29. 74121 Non-Retriggerable OS
74121 one shots can be triggered on either a rising or falling edge.
ECE M. A. Jupina, VU, 2014

30. Example: (a) Show how a 74121 can be connected to produce a
Example: (a) Show how a can be connected to produce a negative-going pulse with a 5 ms duration whenever A1 or A2 is connected to a negative-going trigger.
(b) Modify the circuit so that when a signal “G” goes low it can be used to disable the
Example
Solution:
ECE M. A. Jupina, VU, 2014

31. 74123 Dual One Shot PSPICE Simulation
74123 IC has two retriggerable one shots in the 16 pin chip
A 16 KHz clock is applied to pin 1 (input A) of the first OS to trigger the first OS on a falling edge. The positive-going or high-going pulse on the Q output of the first OS is applied to pin 9 (input A) of the second OS to trigger the second OS on a falling edge. The Q output of the second OS generates a positive-going pulse. The first OS is used as a delay circuit so that the pulse generated at the Q output of the second OS occurs ~20 microseconds after the falling edge of the clock.
When the A input of the OS is used as a trigger input, the other two inputs B and CLR are tied HIGH (see page 2 of the 74123_Data_Sheet.pdf).
The time in which the Q output generates a HIGH or the time in which the Qnot output generates a LOW is given by the following equation for C > 0.01 micro-farads (or 10-8 farads or 10,000 pico-farads)
tw = 0.33 RT Cext
where RT is in kilo-ohms, Cext is in pico-farads, and tw is in nanoseconds.
tw = 0.33 RT Cext
ECE M. A. Jupina, VU, 2014

32. VHDL Nonretriggerable One-Shot
VHDL Code for the implementation of a non-retriggerable, level sensitive one-shot on a FPGA chip.
A 4-bit counter will be used to determine the width of the output pulse. The inputs are a clock signal, trigger, clear, and pulse width value, and the output is Q. When a trigger is detected, the output pulse (Q) goes HIGH and the counter counts down from the pulse width value to zero. The output pulse width is easily adjusted by changing the value loaded into the counter.
3-5: define the inputs and outputs.
11: a PROCESS is used to respond to either the clock or reset inputs
12: a VARIABLE is used to represent the initial (or max) count value
14: the RESET input has overriding precedence (asynchronous input) – if RESET is LOW, COUNT=0
15: if RESET is HIGH then on the next rising edge of the CLOCK begin
16-17: if the TRIGGER goes HIGH and the COUNT=0 then load the initial value into the counter
18: if COUNT=0 then remain at zero
19: else decrease COUNT value by 1
22-23: if COUNT is not equal to 0 then Q is HIGH else Q is LOW (i.e., Q is HIGH while counting down, else it is LOW while COUNT=0).
ECE M. A. Jupina, VU, 2014

33. Simulation of the Nonretriggerable One-Shots
Comparison of this VHDL OS to an IC OS
VHDL OS output does not change state until a rising edge clock signal occurs whereas an IC OS output changes “immediately” when triggered.
The trigger signal for the VHDL OS must be active during a rising clock edge so as to be recognized (the IC OS trigger is an asynchronous signal, i.e., it can occur whenever).
The VHDL OS is level-triggered whereas the IC OS is edge-triggered.
For this VHDL OS, the output pulse goes HIGH on the next rising clock edge as long as the COUNT is not zero; whereas, for an IC OS, the output pulse is “immediately” generated when the trigger is received. For the first trigger, the output pulse occurs ~0.5ms after the trigger input.
This as a nonretriggerable OS since the trigger before the 3ms mark is ignored.
For the VHDL OS, the trigger event must be longer than a clock period or at least occur during the rising edge of the clock to be recognized. At the ~4.5ms mark, the trigger is ignored.
This VHDL OS is level-triggered and not edge-triggered like an IC OS. Before the 9ms mark, the output goes HIGH again since the TRIGGER input remained HIGH. An IC OS would have to receive a rising edge trigger event in order to go HIGH again.
ECE M. A. Jupina, VU, 2014

34. Detecting Edges
Many applications require an OS to be edge-triggered so the VHDL code must be altered to recognized these edge events. The technique in VHDL code that will be implemented is known as edge-trapping and has been used also in programming microcontrollers.
As soon as the edge is detected, the output pulse should be generated. Therefore, the counter value must be loaded as soon as possible after the trigger edge, and the count down to zero begins. If another trigger edge occurs while the output pulse is active, then the counter is reloaded, and the count down to zero begins again, so as to extend the width of the output pulse.
To implement edge-trapping the following will be done: on each active clock edge, the state of the trigger input now and the state of the trigger input when the last active clock edge occurred must be known.
At point c on the above timing diagram, the state of the trigger input now is different from the state of the trigger input when the last active clock edge occurred . Thereby, the counter will be loaded with the initial count value.
ECE M. A. Jupina, VU, 2014

35. VHDL Retriggerable One-Shot with Edge Trigger
VHDL Code for the implementation of a retriggerable edge-triggered one-shot on a FPGA chip. The only differences between this VHDL code and the previous VHDL code is with the logic of the decision process. For this OS, a value is stored that tells us what the trigger was during the last active clock edge. This variable bit is declared in line 11.
When a rising clock edge occurs, one of three conditions exist
1. A trigger edge has occurred and the counter must be loaded with the initial value.
2. The counter is zero and is kept at zero.
3. The counter is not zero and the counter counts down by one.
Recall that the order of the code statements in the PROCESS affects the sequence of operation in the circuit. The code that updates the trig_was variable must occur after the evaluation of its previous condition. For this reason, the conditions necessary to detect a rising edge on trigger are evaluated on line 15. If an edge occurred, then the counter is loaded (line 16) and the variable is updated (line 17) to remember this for the next time. If a trigger edge has not occurred, the code either holds at zero (line 18) or counts down (line 19). Line 21 makes sure that, as soon as the trigger input goes LOW, the variable trig_was remembers this by resetting. Finally, lines create an output pulse during the time in which the counter is not zero.
ECE M. A. Jupina, VU, 2014

36. Simulation of the Edge-Triggered Retriggerable One-Shot
Comparison to Previous VHDL OS
Just as the case before, the output of this OS does not change state until a rising edge clock signal occurs.
Unlike the previous OS, this OS is edge-triggered.
Just as the case before, the trigger signal for this OS must be active during a rising clock edge so as to be recognized.
As with the previous OS, the response is not immediate and the output pulse goes HIGH on the next rising clock edge.
The retriggerable feature is demonstrated at the ~2 ms mark. The trigger goes HIGH and on the next rising clock edge, the count starts again at 5, sustaining the output pulse.
Unlike the previous OS, even after the Q output pulse goes LOW and the trigger is still HIGH, the OS does not generate an output pulse because it is not level-triggered but rather rising-edge-triggered.
Unlike the short trigger pulse around the 6 ms mark, the shorter trigger pulse after the 7 ms mark is HIGH when the rising clock edge occurs and therefore an output pulse is generated.
ECE M. A. Jupina, VU, 2014

37. Final Notes on VHDL OS
To minimize the effects of a delayed output pulse with respect to a rising edge trigger, the clock frequency and the initial value of the count can be increased so that an output pulse of the same width is produced.
An asynchronously triggered OS can be created in VHDL but the output pulse generated will fluctuate in width by up to one clock period.
ECE M. A. Jupina, VU, 2014

38. Example of a Dual One Shot Circuit
The pulse width values for the OS blocks are set by connecting the P_Width wires to either VCC or GND symbols or to switches on the DE2 board.
OS1 and OS2 VHDL code is available at the course website.
trigger (10 KHz)
clock (100 KHz) Q1
ECE M. A. Jupina, VU, 2014

39. OS1 VHDL
-- retriggerable edge-triggered one-shot
-- time delay = delay * clock period
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY os1 IS
PORT ( clock, trigger, reset : IN BIT;
delay : IN INTEGER RANGE 0 TO 15;
q : OUT BIT);
END os1;
ARCHITECTURE a OF os1 IS
BEGIN
PROCESS (clock, reset)
VARIABLE count : INTEGER RANGE 0 TO 15;
VARIABLE trig_was : BIT;
IF reset = '0' THEN count := 0;
ELSIF (clock'EVENT AND clock = '0' ) THEN
IF trigger = '0' AND trig_was = '1' THEN
count := delay; -- load counter
trig_was := '0'; -- "remember" edge detected
ELSIF count = 0 THEN count := 0; -- 0
ELSE count := count - 1; -- decrement
END IF;
IF trigger = '1' THEN trig_was := '1';
IF count /= 0 THEN q <= '1';
ELSE q <= '0';
END PROCESS;
END a;
Note the differences between the code in this slide and slide 35.
ECE M. A. Jupina, VU, 2014