1. Data Conversion Fundamentals
Analog-Digital Converters
Online Seminar
Fall 2002

2. Introduction to A/D Converters
The World Leader in High-Performance Signal Processing Solutions
Introduction to A/D Converters

3. A/D Converter (ADC) Introduction
A/D Fundamentals
Sampling
Quantization
Factors Affecting A/D Converter Performance
Static Performance
Dynamic Performance
ADC Architectures
SAR ADCs
Pipelined ADCs
Flash Type ADC
Sigma-Delta ADCs
High Speed ADC Application Considerations
This presentation will look at the fundamentals of the A/D conversion process including the concepts of quantization and sampling. It will also look at factors which affect both the static and dynamic performance of A/D converters and it will also provide a brief introduction to two types of architectures for deriving A/D converters namely, successive Approximation (SAR) converters and Pipelined A/D converters

4. The Measurement & Control Loop
MUX
ANALOG
SIGNAL
PROCESSOR
A - D
CONVERTER
D - A
MICRO OR
DSP
REFERENCE
Multiplier/Divider
Log Amplifier
rms-dc Converter
F-V/V-F Converter
Operational Amp
Differential Amp
Instrumentation Amp
Isolation Amp n
bits
The basic measurement and control loop measures a process variable and determines what control action needs to be performed based on the processor’s control algorithm. The measurement path takes an analog variable (such as pressure, temperature etc), signal conditions it in the analog domain before applying it to an analog-to-digital converter (ADC). The ADC provides a digital output corresponding to the value of the analog input signal relative to the reference voltage. The resolution of the converter determines the number of bits (n) in the digital representation.
On the control side, the digital word from the processor is converted to an analog value using a digital-to-analog converter (DAC). The number of digital bits which are convereted to an anlog value is determined by the resolution of the DAC.

5. “REAL WORLD” SAMPLED DATA SYSTEMS CONSIST OF ADCs and DACs
The real world problem consists of taking a continuous signal (analog) and applying decisions by means of digital signal processing to the signal. DSP allows for efficient and cost effective means of allocating information (bandwidth, capacity) correctly.
Consider a very basic digital transceiver design consisting of a receive path and a transmit path. In the Rx path a continuous analog signal that represents some element of information is captured at a finite point in time. This signal could be represented as a voltage swing over time. The conversion step occurs when that voltage swing is converted to a digital representation. The resulting digital representation, or codes, can be processed to extract the information content within that signal. Depending on the particular characteristic of that information, certain decisions are made such as route this piece of info to another network node or take a certain action with the receiver at a particular time.
The transmit path is the exact opposite where the info needs to be ‘delivered’ to a real world device.
ADC SAMPLED AND
QUANTIZED WAVEFORM
DAC RECONSTRUCTED
WAVEFORM

6. What is an Analog-Digital Converter?
INPUT
DIGITAL
OUTPUT
RESOLUTION
N BITS
REFERENCE
Analog Input
DIGITAL OUTPUT CODE = x (2N - 1)
Reference Input
Produces a Digital Output Corresponding to the Value of the Signal Applied to Its Input Relative to a Reference Voltage
Finite Number of Discrete Values : 2N Resulting in Quantization Uncertainty
Changes Continuous Time Signal into Discrete Time Sampled Representation
Sampling and Quantization Impose Fundamental yet Predictable Limitations
An analog-to-digital converter produces a digital output which corresponds to the value of the analog input signal. The digital output value corresponds to the relative value of the analog input signal with respect to a fixed reference voltage and, in its most basic form, is determined by the relationship above.
A key element of the transformation from the analog domain to the digital domain is that an analog variable of infinite resolution is now represented by finite discrete values. The analog input is quantized into 2N discrete levels, where N is the resolution of the converter. This results in a quantization error or uncertainity from the A/D conversion process.
The quantization and sampling of the input signal thus impose fundamental limitations on the A/D conversion process. However, these limitations are predictable. Let’s look first at the quantization process.
The A/D conversion process also changes a continuous analog signal in the time domain to a digital signal which is represented by values which occur at discrete intervals. The continuous analog signal is sampled and converted to a digital word at these discrete time intervals.

7. Sampling Process
Representing a continuous time domain signal at discrete and uniform time intervals
Determines maximum bandwidth of sampled (ADC) or reconstructed (DAC) signal (Nyquist Criteria)
Frequency Domain- “Aliasing” for an ADC and “Images” for a DAC
The sampling process is the representation of a continuous time domain signal at discrete and uniform time intervals. The maximum amount of information content, or bandwidth, is determined by the Nyquist sampling theory which states that the maximum bandwidth of a data conversion process is equal to ½ the applied sampling. Also the sampling rate has an affect on where signal aliasing occurs in the frequency domain. In general, for a given bandwidth the higher the sampling rate, the less stringent the filtering needs to be.

8. Any Analog Input in this Range Gives the Same Digital Output Code
Quantization Process
Quantization Process
Representing an analog signal having infinite resolution with a digital word having finite resolution
Determines Maximum Achievable Dynamic Range
Results in Quantization Error/Noise
The quantization process is the representation of the magnitude, in code form, of the continuous analog signal. The number of bits in the quantization process determines the number of discrete levels and, therefore, it determines the smallest resolvable signal. Note, in the diagram above, an analog input in the range shown gives the same digital code. The ratio of this smallest resolvable signal or least significant bit (LSB) to the largest resovable signal (fullscale) defines the maximum achievable dynamic range.
Any Analog Input in this Range Gives the Same Digital Output Code

9. Conversion Relationship for an Ideal A/D Converter
DIGITAL OUTPUT
1 LSB
ANALOG INPUT
1/ /8 3/ / / / /8
001
010
011
100
101
110
111
This shows the conversion relationship for an ideal 3-bit converter. The smallest resolvable signal is 1 LSB which is equal to FS/23 or FS/8. The digital output has 8 discrete values representing a linear transfer function.

10. Quantization Noise
001
010
011
100
101
110
111
1/8
2/8
3/8
4/8
5/8
6/8
7/8 FS
NORMALIZED ANALOG INPUT
DIGITAL OUTPUT
quantization noise error
We have previously talked about quantization errors and how they determine dynamic range etc. This plots shows the profile of the quantization error as it tracks a ramped analog input voltage. At the centre of each of the codes, the quantization error is 0. As the input voltage increases but the digital code remains constant, the quantization error goes negative. At the next code transition, the digital output now jumps ahead of the analog input voltage ramp and quantization error jumps positive. The profile is repeated at each code of the ADC transfer function.
q = 1 LSB

11. Quantization Noise (con’t)
0 volts
+q/2
-q/2
The RMS value of the quantization noise sawtooth is its peak value, q¸2, divided by Ö 3, or q ¸ Ö12
For Sine Wave Full Scale RMS Value is 2(N-1)/Ö2
For Saw Tooth Quantization Error Signal RMS Value is q /Ö12
Thus S/N is x 2N
Expressed in dB as N, where N is the resolution of the A/D converter
Read through Bullets

12. Quantization Noise (con’t)
HARMONICS OF FSIGNAL
(EXAGGERATED FOR CLARITY)
OUTPUT
RMS
QUANTIZATION NOISE
FSIGNAL
FS/2 FS
If the quantization noise is uncorrelated with the frequency of the AC input signal, the noise will be spread evenly over the Nyquist bandwidth of Fs/2.
If, however the input signal is locked to a sub-multiple of the sampling frequency, the quantization noise will no longer appear uniform, but as harmonics of the fundamental frequency
A graphical representation of this RMS error in the frequency domain is shown and is called quantization noise, also referred to as noise spectral density. Remember, this is the quantization error in an ideal converter and is uniformly distributed across frequencies. One thing to note is this is sometimes also called the noise floor. And that the magnitude is dependent on the quantization level (resolution) and sample rate. It’s easy to see that with the same resolution converter, by doubling the sampling rate, the noise floor gets spread over a wider bandwidth. This is called processing gain. By doubling the sample rate, one obtains a 3dB improvement (lowering) of the noise floor or sometimes called “3dB of processing gain”.

13. ADC Resolution vs. Quantization Parameters
This table shows the relationship between the analog input range, or full scale, and the LSB size for different resolutions. The full scale in this case is 2.5V, and a selection of ADCs are quoted as examples.

14. Analog Input Signal Definitions
There are various different types of analog inputs and this slide explains the differences between them.
The first diagram shows a Unipolar, Single Ended analog input signal. The analog input is applied to the VIN pin of the ADC, has an amplitude of the Full scale input voltage (FS) and spans from 0V to +FS. The second diagram shows a Unipolar, Fully Differential analog input signal. In this case, the ADC has a positive and a negative analog input, VIN+ and VIN-. These inputs are driven by two equal signals which span from 0 V to +FS, that are 180° out of phase.
The third diagram shows a Bipolar, Single Ended analog input signal. The analog input is applied to the VIN pin of the ADC, has an amplitude of ±FS/2 and is centered on ground. The fourth diagram shows a Bipolar, Fully Differential analog input signal. In this case, the ADC has a positive and a negative analog input, VIN+ and VIN-. These inputs are driven by two equal signals of amplitude ±FS/2, that are 180° out of phase. The two inputs are centered on ground. The fifth diagram shows a Pseudo Differential analog input signal. In this case, the ADC has a positive and a negative analog input, VIN+ and VIN-. The positive input is driven by a signal of amplitude FS, and the negative input is driven by a small DC voltage to provide an offset from ground or a ‘pseudo ground’ for the VIN+ signal.

15. Unipolar and Bipolar Converter Codes
FS - 1LSB
FS - 1LSB
FS - 1LSB
ALL
ALL
"1"s
"1"s
1 AND ALL "0"S
This slide shows the ideal transfer function of three A/D converters with different digital code representations of an analog input signal. The unipolar transfer function (left-most plot) represents an A/D converter which handles an analog input range from 0 to +FS (Full Scale). The digital output code goes from all 0’s for an analog input voltage of 0V to all 1’s for an analog input voltage of FS–1 LSB. This code format is oftentimes called straight (or natural) binary. The number of discrete values along the way depends on the resolution of the converter.
The middle plot shows the transfer function for an A/D converter which handles a bipolar input range from –FS to +FS. In this case, the digital code is called offset binary where a digital output code of all 0’s represents –FS, a code of 1 and all 0’s (I.e. MSB is 1 and all other bits are 0) represents an analog input of 0V and a code of all 1’s represents an anlog input of FS-1LSB.
Finally, the 3rd plot represents an A/D converter which handles the same analog input voltage range as that just described but represents the digital output via 2’s complement coding. This coding is the same as that just outlined for the offset binary case but has the MSB of the digital word inverted. In effect, this MSB acts like a sign bit which is one for negative signals.
-FS
-(FS - 1LSB)
UNIPOLAR
OFFSET BINARY
2’s COMPLEMENT

16. Factors Affecting A/D Converter Performance - Offset And Gain for Unipolar Ranges
ACTUAL
ACTUAL
GAIN
ERROR
IDEAL
IDEAL
Up to now, the transfer functions shown have been for ideal A/D converters. However, this is not the case in the real world and there are error sources in the A/D converter which will result in a non-ideal transfer function. Let’s look first at two sources of linear error, offset and gain.
First, we will look at the effects of these errors on the transfer function of a unipolar A/D converter. The effect of the offset error is to shift the entire transfer function either up or down (the example shown is for moving the transfer function up, representing a positive offset error). The offset error shifts every code of the A/D converter by an equal amount. Therefore, if the A/D converter has an offset of +2LSB, each digital output code will be shifted by +2LSB from its ideal representation.
The effect of gain error is shown in the right-hand plot. The transfer function shown assumes no offset error. The gain error has the effect of changing the slope of the transfer function. From an absolute value perspective, the gain error shifts each digital output code by a different amount. However, the effect is linear with each output being changed by an equal percentage of its correct value.
ZERO ERROR
OFFSET
WITH GAIN ERROR:
NO GAIN ERROR:
OFFSET ERROR = 0
ZERO ERROR = OFFSET ERROR

17. Factors Affecting A/D Converter Performance - Offset And Gain for Bipolar Ranges
ACTUAL
ACTUAL
IDEAL
IDEAL
ZERO ERROR
ZERO ERROR
This shows the effects of offset and gain errors on A/D converters with bipolar transfer functions. Of note here is the distinction between offset error and zero error. In this case, the true offset error is seen at negative full scale. However, for many bipolar A/D converters, the user is interested in the deviation from ideal at 0V analog input (zero error). With no gain error, the offset error and zero error are the same. However, when gain error effect is shown (as in the right-hand plot), there is a zero error in the A/D transfer function whereas there is no offset error.
OFFSET
NO GAIN ERROR:
WITH GAIN ERROR:
OFFSET ERROR = 0
ERROR
ZERO ERROR = OFFSET ERROR
ZERO ERROR RESULTS
FROM GAIN ERROR

18. DC Specifications (Ideal)
Ideal ADC code transitions are exactly 1 LSB apart.
For an N-bit ADC, there are 2N codes. (1 LSB = FS/ 2N )
For this 3-bit ADC, 1 LSB = (1V/23 = 1/8th)
Each “step” is centered on an eighth of full scale
This slide shows an ideal transfer function for a 3-bit converter.

19. DC Specifications (DNL)
Differential Non-Linearity (DNL) is the deviation of an actual code width from the ideal 1 LSB code width
Results in narrow or wider code widths than ideal and can result in missing codes
Results in additive noise/spurs beyond the effects of quantization
The ideal width for each code is 1LSB but in practice each code width is different from its neighbours. A DNL error is defined as the difference between the ideal 1 LSB step and the actual (real) step as one moves along the transfer function (DNL = actual - ideal). Thus, in the plot shown above, we are measuring the actual width of each code. For example a code with a width of 1.5 lsb would have a DNL of = 0.5 lsb. A missing code would have a width of zero and would have a DNL of = -1.0 lsb. DNL can never be less than -1.0, but has no upper limit.
The effect of DNL error is to add “noise/spurs” to an ideal transfer function. This reduces the accuracy of the conversion beyond the limitations of quantization.

20. DC Specifications (DNL)
DNL error is measured in lsbs.
A given ADC will have a typical DNL pattern.
These patterns will also have an element of randomness to them.
This slide shows how DNL error is typically reported. For each code across the x-axis is the DNL error on the y-axis.
A given ADC design will usually have a typical DNL error pattern. This ADC has repeated pattern of short codes every 512 codes.
There will also be an element of randomness on top of the typical pattern. It depends on the ADC whether the pattern or randomness dominates.

21. DC Specifications (INL)
Integral Non-Linearity (INL) is the deviation of an actual code transition point from its ideal position on a straight line drawn between the end points of the transfer function.
INL is calculated after offset and gain errors are removed
Results in additive harmonics and spurs
INL error is not a measure of code width. It is a measure of the error in a code’s transition point. Ideally, the transition points should occur at exactly the 1/8th, 1/4th, etc voltages. Errors in the converter cause the actual code transitions to deviate from ideal. INL is usually measured with respect to code centres and is the worst deviation of any code centre from an ideal straight line drawn between the endpoints of the transfer function. This ideal straight line is calculated after both offset and gain errors are removed. Thus, in the plot shown above, we are measuring the deviation of its actual transition point from its ‘ideal’ transistion point after gain and offset are removed.
Just like DNL, INL results in a reduction in accuracy of the converter. However, unlike DNL, INL errors can result in added harmonic components. (This will be demonstrated on the next slide.)

22. DC Specifications (INL)
Some typical INL patterns
Bow indicates 2nd order nonlinearity
“S” indicates 3rd order nonlinearity
This slide shows some typical INL patterns. The first graph has a parabolic bow pattern to it. This type of pattern will result in the output signal having an added 2nd harmonic component. This type of bowing pattern can be caused by slew limitation inside of the converter. The second graph shows an “S” pattern. This will results in an additional 3rd harmonic component. The “S” pattern can be caused non-linear capacitance effects in transistors.
In addition to these patterns can be higher order harmonic patterns or combinations of patterns.

23. QUANTIFYING ADC DYNAMIC (AC) PERFORMANCE
Harmonic Distortion
Worst Harmonic
Total Harmonic Distortion (THD)
Total Harmonic Distortion Plus Noise (THD + N)
Signal-to-Noise-and-Distortion Ratio (SINAD, or S/N +D)
Effective Number of Bits (ENOB)
Signal-to-Noise Ratio (SNR)
Analog Bandwidth (Full-Power, Small-Signal)
Spurious Free Dynamic Range (SFDR)
Two-Tone Intermodulation Distortion
Noise Power Ratio (NPR) or Multitone Power Ratio (MPR)
There are two types of performance specification groups that are important in selecting the appropriate ADC. These two groups can be viewed as dynamic and static in nature. Although not completely independent of each other, they can tell you a lot about how the converter operates under certain conditions as well as the ‘quality’ of the ADC design. In the previous slides, we have talked about static performance of A/D converters. Now lets talk about some of the many dynamic performance parameters over the next few slides.

24. Dynamic Testing of A/D Converters
LOW PHASE
JITTER
SINEWAVE SOURCE
A/D CONVERTER ON
EVALUATION BOARD
BANDPASS
FILTER
SAMPLING
CLOCK SOURCE
FFT
ANALYZER
POWER
SUPPLIES
This slide shows the basic elements required to build a tester setup for the dynamic testing of A/D converters. A Fast Fourier Transform (FFT) Analyzer is used to measure dynamic performance of the A/D converter under test.
A Fast Fourier Transform (FFT) Analyzer is used to measure dynamic performance

25. Fast Fourier Transform converts
time
amplitude
this… f1
2f1
3f1
...to this
frequency
amplitude f1
2f1
3f1
A fast Fourier Transform converters an analog time domain signal to a frequency representation in the digital domain as shown above

26. An M-Point FFT
SNR = 6.02N dB
RMS Quantization Noise Level
FFT Floor = 10 log 10 (M ¸ 2)
0 dB
18 dB, M = 128
21 dB, M = 256
24 dB, M = 512
27 dB, M = 1024
30 dB, M = 2048
33 dB, M = 4096
Bin Spacing = D F = FS ¸ M
This plot shows the relationship between the average noise floor of the FFT with respect to the broadband quantization level. Each time M is doubled, the average noise in the delta F bandwidth decresases by 3dB. Note, the effective Noise Floor of an M-Point FFT Is less than the RMS Value of the Quantization Noise
The Effective Noise Floor of an M-Point FFT Is Less Than The RMS Value of the Quantization Noise

27. Actual FFT Plot for AD7484, 14-Bit SAR ADC Sampling at 3MHz
This shows an actual FFT plot for a 14-Bit, 3MSPS SAR ADC. In this case, the input frequency is 1MHz and the sampling frequency is 3MHz.

28. Nyquist Bandwidth & Aliasing
2 Signals that are Mixed Together Produce Sum and Difference Frequency Components
Nyquist Theory Stipulates that the Signal Frequency, FSIGNAL must be < to ½ FSAMPLING to Prevent a Condition Known As “Aliasing”, in which the Difference Component Appears Within the Signal Bandwidth of Interest
Read Through Bullets

29. The Nyquist Bandwidth & Aliasing (FSIGNAL < ½ FSAMPLING)
1 MHz
4 MHz
fsampling
fsampling + fsignal
fsampling - fsignal
signal
passband
3 MHz
5 MHz
fsignal
The Signal Frequency Is < 1/2 the Sampling Frequency and so the Sum and Difference Components Fall Outside (Beyond) the Signal Passband
The Signal Frequency Is < 1/2 the Sampling Frequency and So the Sum and Difference Components Fall Outside (Beyond) the Signal Passband

30. The Nyquist Bandwidth & Aliasing (FSIGNAL > ½ FSAMPLING)
fsampling- fsignal
fsignal
fsampling
fsampling + fsignal
2.5 MHz
1.5 MHz
1 MHz
“Alias”
0.5 MHz
The Signal Frequency Is > 1/2 (approx 2/3) the Sampling Frequency. An “Alias” or False Image is Thus Created that Falls Within the Passband of Interest. There are specific applications where the input signal is bandlimited whereby the A/D converter can actually resolve input frequencies which are beyond the Nyquist frequency. These applications are known as undersampling applications.
The Signal Frequency Is > 1/2 (approx 2/3) the Sampling Frequency. An “Alias” or False Image is Thus Created that Falls Within the Passband of Interest.

31. SINAD, ENOB, and SNR SINAD (Signal-to-Noise-and-Distortion Ratio)
The ratio of the rms signal amplitude to the mean value of the root-sum-squares (RSS) of all other spectral components, including harmonics, but excluding dc
ENOB (Effective Number of Bits)
SNR (Signal-to-Noise Ratio, or Signal-to-Noise Ratio Without Harmonics)
The ratio of the rms signal amplitude to the mean value of the root-sum-squares (RSS) of all other spectral components, excluding the first five harmonics and dc
One of the basic ADC figures of merit is its ability to convert the signal of interest and keep it separate from other noise elements within the signal chain. It’s best defined as the ratio of the rms signal amplitude to the mean value of the root sum squares of all the spectral components. SINAD is this ratio that includes all harmonics. SNR is this ratio but it excludes the first 5 harmonics. ENOB or effective number of bits is another figure of merit and can be derived from SINAD.
It is interesting to note that SNR does depend on signal input level. In an ideal converter, the higher the input level, the higher the SNR. Unfortunately, in the real world the ADC has a maximum input level. Take this plus the fact that it is not an ideal converter, there is a slightly different curve. (solid line vs the dotted line)
======================================
Clipping …in the ADC defines the SNRmax (full scale range)
Delta between are based on the errors introduced in the Rx signal chain…. A perfect converter, quant error exists… other errors intro’d into signal chain (and others within the ADC)… increase this delta.

32. SFDR, THD, and SNR
SFDR = The difference between the rms power of the fundamental and the largest spurious signal in a given bandwidth
THD = The ratio of the rms sum of the first six harmonics to the amplitude of the fundamental
SNR = The ratio of the rms value of the fundamental to the rms sum of all noise components in the Nyquist bandwidth (excluding harmonics)
Spurious free dynamic range and total harmonic distortion are easily explained by this picture. SFDR is the distance between the signal of interest and the highest spur, including harmonics. THD is the distance relative to the signal of interest and the rms sum of a defined set of harmonics. SNR is the distance (ratio) from the signal of interest to the noise floor.

33. ADC LARGE SIGNAL (OR FULL POWER) BANDWIDTH
Full-power bandwidth is defined as the input frequency where the fundamental in an FFT of the output, rolls off to its 3 dB point
ADC’s SHA generally determines the FPBW
FPBW often limited by slew rate of the internal circuitry.
May not be compatible with the converter’s maximum operating rate
Ideally fFPBW >> fs / 2
Many High Speed Converters have fFPBW < fs / 2
Use as a “prerequisite” specification for comparing ADC’s IF undersampling capabilities. But need to consider distortion as well.
The large signal, or full power, bandwidth is defined in MHz representing the region of the ADC performance where the SNR doesn’t degrade beyond 3dB while varying the input frequency. Sometimes called ‘the 3dB point’.
Typically the full power bandwidth is limited by the sampling network within the ADC. The limitation is its ability to slew with the faster signal. At some point the ADC sampling network breaks down. Also, in the past couple of years ADI has introduced a few IF sampling converters (Under sampling) that have input frequency ranges that far exceed the sampling rate, such as the AD9226 (12-bit 65Msps ADC) and the AD9433 (12-bit 125Msps ADC). Each have IF sampling capability (decent performance) with inputs that far exceed 200MHz.
This specification is one of the prerequisites for choosing an IF sampling ADC. One also has to consider the harmonic distortion performance under the same conditions. That’s why it is important to review the typical performance plots that are provided in the datasheet. ADI also offers quick turn ADC ‘vector’ testing in our lab. Just contact one of our FAE’s and tell us your operating conditions and we will send you the fft results within 48 hours. Also we have the ADC FIFO data capture card should you choose to run the evaluations within your lab.
================================
There are different ways to it…. Ad9433 is spec’d with the buffer only… either in SNR degradation or overall bandwidth (when the fundamental falls off 3dB)….

34. Successive Approximation ADC
“Recursive” One-Bit Sub-Ranging Architecture
The successive approximation ADC is one of the simplest architectures used and it is the “work horse” of A/D converters. It is by far the most common type of converter used due to its precision and low-cost. AS can be seen, there are only three blocks in the main loop, a DAC, a comparator, and an SAR register. The way is works is on each clock cycle, the SAR register “tests” one bit at a time, starting with the MSB. For example, it sets the MSB high and all other bits to zero. The DAC then outputs the analog equivalent, (which is mid-scale). The comparator measures whether the analog input is below or above the DAC voltage. If the output of the DAC is less than the VIN voltage, then the output of the comparator will be high and the MSB is kept at a one; if the output of the DAC is greater than the VIN voltage, then the output of the comparator will be low and the MSB is reset to zero. This information to the SAR register and this value is maintained for the MSB of the DAC for the rest of the routine. On the next clock cycle, the 2nd MSB is set to one. The DAC output will now either be 1/4 or 3/4 or full scale depending on the MSB. It does this repeatedly until all bits are resolved. Note: this ADC architecture requires a held dc voltage as its input, which is the reason for the SHA.
As you can imagine, this type of architecture is very efficient in terms of power and size. The main disadvantage is that the sample rate is dependent on the resolution.

35. Successive Approximation ADC

36. How a Successive Approximation A/D Converter Works
Rising/Falling Edge of Convert Start Pulse Resets Logic
Falling/Rising Edge Begins Conversion Process
Bit Comparisons Made on Each Clock Edge
Conversion Time Equals Number of Comparisons (Resolution) Times Clock Period
The Accuracy of Conversion Depends on the DAC Linearity and Comparator Noise
Read Through Bullets

37. How Successive Approximation Works
EXAMPLE : ANALOG INPUT = 6.428V, REFERENCE = V
MSB
5.000V
2SB
2.500V
3SB
1.250V
LSB
0.625V
VIN > 5.000V
VIN > 6.875V
VIN > 6.250V
VIN > 7.500V
YES 1 NO
This example works through a 4-bit successive approximation routine for an input of 6.428V for an A/D converter with a 10V fullscale. When the MSB of the D/A converter is turned on, the output of the D/A converter is 5V. This is lower than the VIN voltage and, therefore, the bit is retained as a 1. The next bit is then turned on, resulting in a D/A converter output of 7.5V. This is greater than the VIN voltage so this bit is rejected and returned to a 0. The third MSB is then tried, with a resulting output voltage of 6.25V from the D/A converter. This is less than the VIN voltage so this bit is retained as a 1. Finally, the LSB of the D/A converter is turned on to give an output voltgae of 6.875V. This makes the D/A output voltage greater than Vin and the LSB is rejected and returned to a 0. The successive approximation routine is now complete with a resultant digital word of 1010 in the SAR register, representing the digital output word from the SAR ADC.

38. Successive Approximation ADC
Advantages to SAR A/D converters
Low Power (12-bit/1.5 MSPS ADC: 1.7 mW)
Higher resolutions (16-bit/1 MSPS)
Small Die Area and Low Cost
No pipeline delay
Tradeoffs to SAR A/D converters
Lower sampling rates
Typical Applications
Instrumentation
Industrial control
Data acquisition
This example works through a 4-bit successive approximation routine for an input of 6.428V for an A/D converter with a 10V fullscale. When the MSB of the D/A converter is turned on, the output of the D/A converter is 5V. This is lower than the VIN voltage and, therefore, the bit is retained as a 1. The next bit is then turned on, resulting in a D/A converter output of 7.5V. This is greater than the VIN voltage so this bit is rejected and returned to a 0. The third MSB is then tried, with a resulting output voltage of 6.25V from the D/A converter. This is less than the VIN voltage so this bit is retained as a 1. Finally, the LSB of the D/A converter is turned on to give an output voltgae of 6.875V. This makes the D/A output voltage greater than Vin and the LSB is rejected and returned to a 0. The successive approximation routine is now complete with a resultant digital word of 1010 in the SAR register, representing the digital output word from the SAR ADC.

39. Pipelined Sub-ranging ADC
Conversion divided into discrete stages thus causing pipeline delay
1st Stage ADC is 6-bit FLASH
2nd Stage ADC is 7-bit Flash
Total resolution is 12 bits (one bit used for error correction)
The subranging architecture is a great way to achieve higher resolutions. For example a 12-bit flash ADC would need (212-1 = 4095) comparators, but a sub-ranging ADC only needs ( = 190) comparators. The additional circuitry needed is much less than the fewer comparators needed. The reduction in circuitry is what provides the lower power and die size.
The operation of a sub-ranging ADC is much like the successive approximation ADC except it resolves more than one bit at a time. For this example, the ADC does a rough 6-bit conversion, (result is code X). The result of this conversion is passed to a DAC which outputs a “perfect” analog reference for code X. The difference between the actual analog input and the “perfect” output of the DAC is passed to second ADC which makes fine conversion.
The output of the two conversions is combined using logic into one 12-bit word. Note, an extra bit of resolution is needed in the second ADC in order to perform error correction. Error correction is needed because of offsets between the two stages.

40. Pipelined Sub-ranging ADC
This slide shows an example of how a sub-ranging ADC works. First, the rough ADC does a conversion. The DAC creates a reference voltage which is compared to the original analog signal. The resulting residue signal is then gained up and passed to a second “fine” ADC. The entire range of the second converter should equate to one “step” of the first ADC. After the second ADC is finished the complete word is put together. For this example, the output would be Note: no error correction is show in this example.

41. Pipelined Sub-ranging ADC
Advantages to Pipelined Sub-ranging A/D converters
Higher resolutions at high-speeds (14-bits/105 MSPS)
Digitize wideband inputs
Tradeoffs to pipelined sub-ranging A/D converters
Higher power dissipation
Larger die size
Typical Applications
Communications
Medical imaging
Radar
This slide shows an example of how a sub-ranging ADC works. First, the rough ADC does a conversion. The DAC creates a reference voltage which is compared to the original analog signal. The resulting residue signal is then gained up and passed to a second “fine” ADC. The entire range of the second converter should equate to one “step” of the first ADC. After the second ADC is finished the complete word is put together. For this example, the output would be Note: no error correction is show in this example.

42. Flash or Parallel ADC
2N-1 comparators form the digitizer array, where N is the ADC resolution
Analog input is applied to one side of the comparator array, a 1 lsb reference ladder voltage is applied to the other inputs.
The comparator array is clocked simultaneously and decides in parallel.
Output logic converts from thermometer code to binary
The flash ADC architecture is probably the faster ADC architecture available. The reason for this is its parallel but shallow configuration.
The way it works is by first setting up reference voltages. This is usually done with a series connected resistor ladder. These reference voltage are what will correspond to code transition points in the ADC. In this case, the reference voltages are: 1/16, 3/16, 5/16, 7/16, 9/16, 11/16, 13/16. Notice that for M possible output codes, there are only M-1 reference points (and comparators). The reason for this is the first reference voltage defines two states (above and below), while each additional one only adds one additional state (middle).
Once the references are set, an analog voltage can be applied. Depending one what the analog voltage is, some comparators will be high and some will be low. The transition point correponds to what the output code will be. For example, if the analog input is at 1/2 scale, the bottom four comparators will be high and the top three will be low. The encoder logic recognizes this and will then output 100.
One interesting note, is that this architecture does not require a held dc input. This is because the comparators are always running and their output data can be latched in a single instance in time. However, in some instances when fast moving analog inputs are being digitized, a track and hold circuit can help improve performance and reduce “sparkle” codes.

43. Flash or Parallel ADC Advantages to Flash A/D converters
Fastest conversion times (up to 1 GSPS)
Low data latency
Tradeoffs to Flash A/D converters
Higher power consumption
High capacitive input is difficult to drive
Typical Applications
Video digitization
High-speed data acquisition
The flash ADC architecture is probably the faster ADC architecture available. The reason for this is its parallel but shallow configuration.
The way it works is by first setting up reference voltages. This is usually done with a series connected resistor ladder. These reference voltage are what will correspond to code transition points in the ADC. In this case, the reference voltages are: 1/16, 3/16, 5/16, 7/16, 9/16, 11/16, 13/16. Notice that for M possible output codes, there are only M-1 reference points (and comparators). The reason for this is the first reference voltage defines two states (above and below), while each additional one only adds one additional state (middle).
Once the references are set, an analog voltage can be applied. Depending one what the analog voltage is, some comparators will be high and some will be low. The transition point correponds to what the output code will be. For example, if the analog input is at 1/2 scale, the bottom four comparators will be high and the top three will be low. The encoder logic recognizes this and will then output 100.
One interesting note, is that this architecture does not require a held dc input. This is because the comparators are always running and their output data can be latched in a single instance in time. However, in some instances when fast moving analog inputs are being digitized, a track and hold circuit can help improve performance and reduce “sparkle” codes.

44. FIRST-ORDER SIGMA-DELTA ADC
CLOCK
Kfs fs
INTEGRATOR
VIN ò
DIGITAL
FILTER
AND
DECIMATOR å A +
N-BITS + _ _ fs
LATCHED
COMPARATOR
(1-BIT ADC) B
+VREF
1-BIT,
Kfs
1-BIT DATA
STREAM
1-BIT
DAC
–VREF
SIGMA-DELTA MODULATOR

45. OVERSAMPLING, DIGITAL FILTERING, NOISE SHAPING, AND DECIMATIONfs
QUANTIZATION
NOISE = q / 12
q = 1 LSB
Nyquist
Operation
ADC fs 2
Kfs 2 fs
DIGITAL FILTER
REMOVED NOISE
ADC
DIGITAL
FILTER
Oversampling
+ Digital Filter
+ Decimation B
DEC fs
Kfs 2 fs
REMOVED NOISE SD
MOD
DIGITAL
FILTER
DEC
Oversampling
+ Noise Shaping
+ Digital Filter
+ Decimation C

46. DEFINITION OF "NOISE-FREE" CODE RESOLUTION
FULLSCALE RANGE
RMS NOISE
EFFECTIVE
RESOLUTION =
log2
BITS
NOISE-FREE
CODE RESOLUTION =
log2
FULLSCALE RANGE
P-P NOISE
BITS
P-P NOISE = × RMS NOISE
0.4uVrms
20mV
16.5bits
NOISE-FREE
CODE RESOLUTION =
log2
FULLSCALE RANGE
6.6 × RMS NOISE
BITS
= EFFECTIVE RESOLUTION – BITS

47. SIGMA-DELTA ADCs Advantages to Sigma-Delta A/D converters
High resolutions and accuracy (24-bits)
Excellent DNL and INL performance
Noise shaping capability
Tradeoffs in Sigma-Delta A/D converters
Limited input bandwidth
Slower sampling rates
Typical Applications
Precision data acquisition and measurement
Medical instrumentation

48. High Speed ADC Time Domain Specifications Considerations
Aperture Jitter and Delay
ADC Pipeline Delay
Duty Cycle Sensitivity
DNL Effects
The last section of this tutorial is a discussion about specifications relating time based elements (time domain) to ADC performance. Note that all three specifications apply to Pipelined ADCs while SAR ADCs do not usually have any clock duty cycle sensitivities and have no pipeline delays.

49. EFFECTS OF APERTURE AND SAMPLING CLOCK JITTER
Most systems assume the signal is sampled uniformly
Clock noise leads to non-uniform sampling (i.e. jitter)
Jitter leads to SNR degradation for high frequency inputs:
With the most of the high performance high resolution ADCs in the marketplace today, one limitation that one runs into is performance related to the amount of jitter present on the input clock. If there is variation in the rising edge of the input clock (“trigger point”) then this variation gets ‘transferred’ into output uncertainty or noise. And as we have seen earlier, this noise affects overall SNR. In fact, jitter can be the primary limiting factor in an IF sampling scheme, not the ADC itself.
=======================
Increase clock drive… square wave look a like…. Increases the slew rate and you get an improvement in jitter perf. Assuming constant noise on DC threshold and clock input signal

50. SNR DUE TO APERTURE AND SAMPLING CLOCK JITTER
To explain what we mean, this chart shows the theoretical relationship between clock jitter and the resultant SNR. So in other worlds, if one had a perfect 16-bit ADC but the clock input had 10ps of jitter, the best SNR achieved in the system is roughly 50dB with a 100MHz full scale single tone input signal.

51. EFFECTIVE APERTURE DELAY TIME
Typically not an issue in frequency domain applications
May vary slightly among devices of same product due to variations in SHA bandwidth and CLK prop. delays
Aperture delay is the delay between when the rising edge of the input clock triggers the capture (or Hold in a sample and hold block) of the signal vs the actual time the signal is captured. This is usually very critical in applications where there is a correlation between time and the signal (Time domain applications) such as CCD’s and other video imaging systems.
==================================================
Good for time “correlated” signals like CCD or other video – time domain

52. ADC LATENCY OR PIPELINE DELAY
Many High Speed ADC’s, such as subranging types, use pipeline architectures to:
Reduce chip size, and power consumption
Allows multiple samples to be converted simultaneously in ADC
Results in fixed delay between Sampled Input and corresponding digital output.
ADC latency is the time in number of clock cycles it take to obtain an output code that represents the input signal level at time equals zero. Many high speed, high resolution ADCs use this approach, hence there is pipeline delay. It could be a critical spec if you have a control loop based on this converter, such as an AGC loop or feed-forward pre-distortion. A/D converters implemented using SAR rtechniques do not have pipeline delays associated with them.

53. ADC DUTY CYCLE SENSITIVITY
High Speed ADCs are often sensitive to duty cycle of the CLK input
CLK oscillators are usually specified as 40/60 or 45/55
Digital Specifications of datasheet provide a minimum CLK HIGH/LOW period (nsec) to achieve rated performance.
Some datasheets show SNR/THD graphs as a function of duty cycle
Note, ADC also has minimum specified sample rate
Lastly, the duty cycle of the clock is also sensitive and affects ADC performance. Most ADCs today utilize both edges of the clock so any deviations outside the usual +/-10% could prove harmful to AC performance. With that said, ADI has incorporated a clock duty cycle stabilizer option (some ADCs have them always on). The graph shows an example of the AD9226 with the stabilizer option enabled and disabled. Once again, A/D converters implemented using SAR techniques
do not have an issue with duty cycle and usually operate down to very low clock frequencies.
===================================
Settling time issue… most ADCs us both phases of the clock … track and hold mode…. Time for the hold to settle out could be tight.
Use the rising edge…

54. DNL ERRORS LIMIT IDEAL NOISE AND SPUR FLOOR PERFORMANCE
Ideal ADC code transitions are exactly 1 LSB apart. DNL is the deviation from this value.
Results in additive noise/spurs beyond the effects of quantization
Limits ultimate achievable SNR and low level signal SFDR performance
Predictable for a given device once error transfer function is known.
DNL error pattern varies among devices of a given product
Dynamic correction techniques include adding “dither” or element shuffling
Let us dig a little deeper on the effects DNL has on the AC performance of the ADC. So what are the effects of poor DNL? It is an additive affect resulting in increased noise/spur content within the frequency spectrum. Added noise to the ideal noise floor results in lower SNR performance and if using a low level input signal, SFDR would also suffer. This error is predictable over the transfer function but unfortunately, it varies from device to device. Consequently, dynamic correction techniques such as dither (external low frequency input source) or element shuffling are used to remove this code dependent quantization noise.
============================
In addition to quantization noise, there are additional noise elements do to transfer function errors.
Looks like Code dependent quantization noise…. To really see how this affects SNR, you need to RMS the DNL.

55. Example : AD9433 SFDR SFDR ENABLED DISABLED
An example of element shuffling is the AD9433, 12-bit 125Msps ADC. Actually, it is defined as an SFDR enhancement option. AS you can see by enabling element shuffling, the linearity errors get ‘randomized’ across the transfer function, thus resulting in a more linear DNL/INL plot. This randomization effect is analogous to ‘trimming’ up the code dependent errors.

56. Example : AD9433 SFDR SFDR ENABLED DISABLED
Looking at the frequency spectrum, you can see the effect. Less spur content is seen. The energy within those spurs are randomly spread over the entire frequency band resulting in a 3dB improvement in SFDR with little impact to SNR.
Encode = 105Msps
Ain = 70MHz, -0.5dBFs

57. Example of Data Sheet Specifications for AD9430 ADC
This is an example of a data sheet for a wideband 12-bit/170 MSPS ADC. This data sheets contain extensive DC, AC, time domain, and frequency domain parameters specified up to Nyquist operating conditions. Data sheets generally also contain the applications information needed to insure the device will perform to its rated specifications in the end-system.

58. Example of Data Sheet Specifications for AD7476 ADC
This is an example datasheet for a 12-bit, 1MSPS ADC – the AD7476. This shows a breakout of both the dynamic performance specifications, including SINAD, SNR, THD and Full Power Bandwidth and the DC Accuracy specifications such as Integral Nonlinearity (INL), Differential Nonlinearity (DNL), Offset and Gain Errors. Not shown on this screen shot is that this performance is achievable with less than 4mW of power dissipation.

59. For complete information on the World’s most extensive line of
A/D converters visit
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