1. Electronic Counters

2. Abstract
Electronic counters come in two flavors: asynchronous and synchronous. Asynchronous counter encode a count sequence by directly connecting flip-flops and allowing the clock-pulse to ripple through the cascade. Synchronous counters use a common clock and logic between flip-flops to encode the count sequence. Asynchronous counters are simpler because they do not require logic gates, but any latency will scale linearly with respect to the number of bits. Synchronous counters are more complex but constrain the latency. If the cumulative latency is greater than the maximum allowable cycle time, then a synchronous architecture is preferable. If the application is not sensitive to false errors produced by latency, however, an asynchronous counter alone or with over-clocking (in the event that cumulative latency is greater than the cycle time) may be feasible. Alternatively filters, such as a strobing circuit, can be used to remove erroneous outputs caused by latency from the output.

3. Memory devices : Flip flops
Systems : Counters
Output
Memory devices : Flip flops
Input
Flip
Flop
Clock
Logic gates
Input 2
Output’
Transistors
And diodes - + N P
Solid State Physics

4. Electronic counter Addressable Memory device I/O signals Flip flop
Wires
Counter
Architecture
Asynchronous
Synchronous

5. A bit is a two-state object,
such as a flip-flop.
Electronic flip-flop
State 1

6. A collection of n bits can encode 2^n information levels (states).1
All possible information levels for three bits
000
001
010
011
100
101
110
111

7. Each information level can represent a number.
State 1
All possible information levels for three bits
000
001
010
011
100
101
110
111 1 2 3 4 5 6 7 8

8. Bits oscillating with proportional frequencies encode count sequence.
000
001
010
011
100
101
110
111 1 2 3 4 5 6 7 8
Bit 1
Bit 2
Bit 3

9. Counter system architecture connects bits (JK flip-flops) to produce this frequency pattern.1
Bit 2
Bit 3

10. Asynchronous

11. Couple two two bits so that inverse output from bit 1 is trigger for bit 2.
Inverter

12. Bit 1 output and inverted output
Trigger 1
Output 1
Output 1
Inverted

13. Bit 1 inverse output serves as clock for bit 2
Bit 1 inverse output serves as clock for bit 2. Triggers state change at positive going transitions.
Output 1
Inverted
Trigger 2
Output 2

14. 2 outputs of proportional frequency produce the count sequence00 01 10 11 1 2 3 4

15. But if there is a delay between command to toggle and response …
Latency
JK Flip-Flop
“Trigger”
“Trigger”
Toggle:
Change State
AND
“Enable”
Bit
State
Delay, D

16. … latency scales linearly wrt # of bits
Ideal
Observed
Clock 1 D
Bit 1
Clock 2 D
Bit 2
Accumulated latency = n*d, for counter of n bits

17. And results in an erroneous count.
Ideal
Observed
Clock 1 D
Bit 1
Clock 2 D
Bit 2
01 (2)
10 (3) 01 01
00 (1) 10

18. But if accumulated delay occurs before clock returns to low state …
Accumulated delay = (n-1)*d
Clock n
Accumulated delay = (n)*d
Bit n

19. … let error ripple through the system when clock is high, then read output when the clock is low.
“Strobing” circuit
Clock 1
Low enable is True
Bit 1
Clock 2
Bit 2 01 10
Then read bits to produce correct output

20. Problem: delay limits clock speed …
Clock frequency must be set allow cumulative delay to ripple through cascade of bits during the high level of the trigger.
Thus, the length of ½ cycle > length of cumulative delay
Clock n
Cumulative delay = (n)*d
Bit n

21. synchronous counter that avoids “rippling” is preferable.
In applications where false outputs from propagation delay produces errors and where speed is important,
synchronous counter that avoids “rippling” is preferable.

22. Synchronous

23. Couple enable to logic gate that processes output from prior bits : when all prior bits are high, then 1 passed to bit and output toggles.
JK Flip-Flop
“Trigger”
Toggle
Output
AND
“Inputs”
Prior
Bits

24. Synchronous counter: each bit holds its state until all preceding bits are high and positive clock pulse. Q1 Q2 Q3
And
High 1 2 3
Clock
Clock Q1 1 1 1 1 Q2 1 1 Q3 1
000
001
010
011
100
101
110
111 1 2 3 4 5 6 7 8

25. Bits flip simultaneously, with same latency : D: latency of flip-flop
no false outputs
Clock
Bit 4 trigger 1
D: latency of flip-flop
Bit 1 1 1
Bit 2
Bit 4 enable:
Logic gate inputs 1 1
Bit 3 1 1
Bit 4
Bit 4 state 1
Time 1
Time 2: Flip

26. Compare synchronous to asynchronous …
Clock D
Grows to 4*D
Bit 1
Bit 2
Bit 3
Bit 4
Latency for synchronous fixed and no false outputs but is synchronous is 4*D by 4th flip-flop, necessitating measures (“strobing circuit”) to prevent errors and thus limiting speed.

27. Knowing … Clock Clock Clock n Bit n
1. Cumulative latency for asynchronous counter
2. Minimum acceptable clock speed
Clock
Clock
Maximum acceptable
cycle time
Clock n
Small clock speed has long cycle time …
Clock is as long as one can make it …
Bit n
Latency

28. Decision … Synchronous Architecture Asynchronous Architecture
Is cumulative latency > maximum cycle time?
Yes No
Do false outputs resulting from latency cause errors?
Synchronous
Architecture
Asynchronous
Architecture No
Small clock speed has long cycle time …
Clock is as long as one can make it …
Yes
Is cumulative latency < ½ maximum cycle time?
With strobing circuit to “block” output during high level in clock cycle. No
Yes