1. Capacitance Sensor Project
Goal: Creation of a digital capacitance sensor circuit where a variation in capacitance changes the frequency or period of oscillation of a timer circuit. A digital circuit then measures this change in the time period and displays an integer value between 0 to 99 (base 10) to indicate the amount of capacitance. A capacitance value of Cmin would be indicated by a value of 0 and a value of Cmax would be indicated by a value of 99. The current maximum value will be stored by the sensor circuit and displayed on the seven-segment LED displays on the DE2 board.
ECE M. A. Jupina, VU, 2015

2. Capacitance Sensor Project
Sports Applications
Tank Application a H d b
Example Applications:
Variation in the distance between the “plates” of a parallel-plate capacitor is used to measure the amount of impact on a Football Blocking Sled or in a Boxing Glove or Bag. The conductive plates and the dielectric material between the plates are made of a flexible (foam) material.
Variation in the “effective dielectric constant” of the capacitance between a coaxial rod and the wall of a cylindrical tank is used to measure the amount of material in the tank.
Epsilonr – relative permittivity or dielectric constant of the material between the two conductors of a capacitor.
Epsilono – permittivity of air = 8.85x10-12 F/m
Project Setup: A variation in capacitance changes the frequency or period of oscillation of a timer circuit. A digital circuit measures this change in frequency (or time period) and displays a value between 0 to 99 to indicate the amount of impact or volume in an application. Cmin (or a value of 0) would indicate no impact or an empty container, whereas, Cmax (or a value of 99) would indicate maximum impact or a full container.
OUTPUT
0 - 99
7-segment displays
variable
frequency or
period
555 Timer
ECE M. A. Jupina, VU, 2015

3. Application of Your Capacitance Sensor
Assume that you are designing an impact sensor for a boxing glove where you want to capture only the maximum impact of the glove on a boxing bag during a training session.
For a range of possible impacts, assume that no impact on the capacitance sensor is a value of Cmin, whereas the maximum possible impact on the capacitance sensor by a boxer such as Mike Tyson would be a value of Cmax. The display on the glove would indicate a value of 0 for no impact and a value of 99 if Mike Tyson hit a boxing bag with the glove.
A reset button will also be available to clear the sensor so that the maximum impact value can again be captured.
ECE M. A. Jupina, VU, 2015

4. Specifications of Your Capacitance Sensor
Assume that the capacitance of the sensor varies as a linear function of the impact applied to the boxing glove.
The maximum capacitance that can be measured by the sensor is
Cmax = 4 Cmin
Therefore, the range of capacitance that is to be measured is
DC = Cmax - Cmin = 3 Cmin
When C=Cmin, the period of the timer circuit will be Tmin, whereas when C=Cmax the period of the timer circuit is Tmax since the period of the timer circuit increases as the RC time constant time increases. The timer circuit will be a 555 timer.
ECE M. A. Jupina, VU, 2015

5. Specifications of Your Capacitance Sensor
An 8-bit counter in the Timer_Count block will be used to measure the period of oscillation of the timer circuit.
The clock frequency used by the 8-bit counter can be one of the following frequencies: 1 KHz, 10 KHz, or 100 KHz.
Use the following Cmin values depending on your lab station #:
Cmin = mF, for lab stations 1, 4, 7, 10, 13, & 16
Cmin = 0.01 mF, for lab stations 2, 5, 8, 11, 14, & 17
Cmin = 0.1 mF, for lab stations 3, 6, 9, 12, 15, & 18
A subtraction circuit will be used to null the value of the counter when T=Tmin by offsetting the output value such that it equals 0 when T=Tmin. Thereby, a value of 99 at the output represents the time period DT = Tmax – Tmin (Note: DT is directly proportional to DC).
The 8-bit counter counts from 0 to
ECE M. A. Jupina, VU, 2015

6. Block Diagram of the Capacitance Sensor
1KHz
10KHz or
100KHz
50 MHz Oscillator
When C = Cmin, Output = 0
When C = Cmax, Output = 99
CLK_DIV
Reset
TIMER_COUNT
Seven_Seg_Display -
f, T
f/2, 2T
0 to 99
OFFSET
ECE M. A. Jupina, VU, 2015

7. Quartus Block Diagram File to Verify Functionality
Screen capture of capsensor1.bdf is shown.
Go to insert symbol and Vcc can be found in the “other” library under primitives
Go to insert symbol and JKFF can be found in the in the storage library under primitives
ECE M. A. Jupina, VU, 2015

8. Quartus II Simulation
On this time scale, the details of this signal are not
seen since its period is too small. ? ? ?
Input signal is the 555 timer output signal
Input_2x signal is the 555 timer output signal divided by 2
Offset input is a constant
cout signal is the output of the Timer_Count block
Output is the final value shown in an unsigned decimal format (right-click on “Output” and set under the properties menu)
count_temp < count_final
so count_temp value
is not captured since only
the max value is captured
Counter in Timer_Count
block is counting
Output in Timer_Count block
is again increasing since
count_final > count_temp
ECE M. A. Jupina, VU, 2015

9. Prelab Assignment Pre-Lab
For your given Cmin and Cmax values, determine the possible values of DT (=RDC) given that the R values will be either in the KW, 10’s KW, or low 100’s KW range (possible resistor values are 1K, 2.2K, 3.3K, 4.7K, 10K, 22K, 33K, 47K, and 100K and can be combined in series or parallel configurations to achieve specific values). Given the possible DT values and the fact that an 8-bit counter will be used, what clock periods are possible?
For your possible DT values, design a 555 timer circuit to meet the specifications described in slides 4 and 5. Select one of these circuits as your final design.
Finish the Timer_Count VHDL code shown on the next page such that
If the reset is LOW, clear all signal inputs (lines 24-26).
On each rising edge of the clock signal, if the timer_2x input is HIGH, then increment the count value by 1 and temporarily store the count (count_temp), otherwise clear the count value (lines 28-33).
Store only the maximum count value (count_final) (lines 35-39).
The output of count value (count_out) is the final count value (line 43).
The unfinished Timer_Count VHDL code is given at the course web site.
ECE M. A. Jupina, VU, 2015

10. Unfinished Timer_Count VHDL Code
The unfinished Timer_Count VHDL code is given at the course web site.
ECE M. A. Jupina, VU, 2015

11. Additional Guidelines for the Timer Circuit Design
1. DT = R * DC where the time period DT  is also equal to 99 clock periods (possible clock periods, Tclk, are 1ms, 10ms, or 100ms).  Depending on the DC value (3*Cmin) given to you and the R value that you choose will determine which Tclk values are possible. 2.  Once possible DT values are known, possible Tmin and Tmax values are thereby known.  Given a certain Tmin or Tmax value, you should be able to design a 555 timer circuit that oscillates with a period of Tmin or Tmax depending on the C value in the circuit.  The R values in these timer circuits will be approximately the same value (or at least the same-order-of-magnitude) as the R value that was first determined in guideline 1.
3.  For the 555 timer circuit, use the formulas for the period of oscillation (T) from the topic 5 class lecture ppt file.
ECE M. A. Jupina, VU, 2015

12. Lab Procedure Work to be preformed in the Lab:
Compile and simulate a sensor circuit like the one shown in slide 7 (call it capsensor1.bdf). Your simulation should be similar to the one depicted in slide 8.
Start a new project. Add a timer input signal, a Reset signal (KEY3), offset value (SW7-SW0), a CLOCK signal (derived from the 50 MHz signal and the clk_div block), a block to drive the seven segment LED output displays, and pin assignments to the previous design (call it capsensor2.bdf now) and compile it (no need to simulate this design since you verified its functionality in capsensor1 project). After successful compilation, download the design to the DE2 board and then verify the operation of your capacitance sensor over a range of capacitance values.
REMEMBER: BEFORE COMPILING, SET UNUSED PINS AS INPUTS (this will be important especially for the DE2 board to prevent damage to the board!)
ECE M. A. Jupina, VU, 2015

13. Simple ADDER VHDL Code
When the AddSub line is LOW, the addition operation is performed; otherwise, the subtraction operation is performed.
ECE M. A. Jupina, VU, 2015

14. Figure 6.25. A BCD-to-7-segment display code converter.w f b c w 1 d w g 2 e e c w 3 f g d
(a) Code converter
(b) 7-segment display w w w w a b c d e f g 3 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
(c) Truth table
ECE M. A. Jupina, VU, 2015

15. Figure 6.47. Code that represents a BCD-to-7-segment decoder.
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY seg7 IS
PORT ( bcd : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
leds : OUT STD_LOGIC_VECTOR(1 TO 7) ) ;
END seg7 ;
ARCHITECTURE Behavior OF seg7 IS
BEGIN
PROCESS ( bcd )
CASE bcd IS abcdefg
WHEN "0000" => leds <= " " ;
WHEN "0001" => leds <= " " ;
WHEN "0010" => leds <= " " ;
WHEN "0011" => leds <= " " ;
WHEN "0100" => leds <= " " ;
WHEN "0101" => leds <= " " ;
WHEN "0110" => leds <= " " ;
WHEN "0111" => leds <= " " ;
WHEN "1000" => leds <= " " ;
WHEN "1001" => leds <= " " ;
WHEN OTHERS => leds <= " " ;
END CASE ;
END PROCESS ;
END Behavior ;
ECE M. A. Jupina, VU, 2015

16. Hexadecimal to 7-Segment Decoder
Outputs
Input
ETC.
ECE M. A. Jupina, VU, 2015

17. Unfinished Seven_Seg_Display VHDL Code
The unfinished Seven_Seg_Display VHDL code is given at the course web site.
File, Create/Update, Create Symbol Files for Current File will compile the VHDL code and generate a symbol that can be placed in a BDF (block diagram file) in Quartus.
ECE M. A. Jupina, VU, 2015

18. Clock Divider for DE2
File, Create/Update, Create Symbol Files for Current File will compile the VHDL code and generate a symbol that can be placed in a BDF (block diagram file) in Quartus.
When you simulate your design in Quartus, don’t use the Clock Divider block since simulation times will be exceedingly long since everything will be based on a 50 MHz clock signal (20 ns period!!!!!). Instead define the 10 KHz signal, 1 KHz signal, etc. in the vector waveform file.
The clock_50MHz input is connected to pin number N2.
ECE M. A. Jupina, VU, 2015

19. DE2_pin_assignments.csv File
To import pin assignments for the DE2 board to your project, go to Assignments, Import Assignments, add the *.csv file, OK
ECE M. A. Jupina, VU, 2015

20. Lab Measurement Details
Measure the values of the capacitors that you are using for testing on a capacitance meter.
On the scope, also measure the period of oscillation (T) of the output signal from the timer circuit under the different capacitance values.
Make a table showing the C value, T value, and the output value shown on the display. Demonstrate through calculations that the C, T, and the output values are correct. If slight differences exist, what are the possible sources of error?
Demonstrate that if the capacitance value is reduced, the output display does not change (i.e., only the max value is displayed). After pressing the reset button, does the display now show a value consistent with the current capacitance value?
Finally, verify the functionality of your design by capturing the same signals within your design as shown on slide 8 using the Signal Tap II Logic Analyzer.
ECE M. A. Jupina, VU, 2015

21. Settings for Signal Tap II Logic Analyzer
@1: EP2C35 (0x020B 40DD)
For the above example, the settings are
Captured signals: RST, Rec_Play, CLK_10K, we, Start, Cout, Bus, AddSub, Done
Trigger: Cout = 0000
Hardware: USB-Blaster
Device: EP2C35
Clock: CLK_100K
Data Sample Depth: 512
ECE M. A. Jupina, VU, 2015

22. Example of Signals Displayed in Signal Tap II
@1: EP2C35 (0x020B 40DD)
ECE M. A. Jupina, VU, 2015

23. An Example Design Illustrating the Mapping of Multi-Bit Connections
Example shows the 8-bit word (vector) signals coming out of a counter and into an LCD display drive. Buses will be represented as thicker wires with vector labels (example, q[7..0]) denoting multi-bit words. These multi-bit words also be mapped to single-bit inputs by naming the wires q[7], q[6], q[5], etc.
ECE M. A. Jupina, VU, 2015