1. Raja Ramanna Centre for Advanced Technology
Development of MHz Solid State Wide Band RF Power Amplifiers for the CLIC injector pre-buncher *
Purushottam Shrivastava, P. Mohania, A. Mahawar, P.D. Gupta
Raja Ramanna Centre for Advanced Technology
Indore, India
CLIC Workshop Jan 26-30, 2015
* DAE (India) CERN Collaboration under NAT Protocol

2. Motivation
Under DAE (India) CERN collaboration in Novel Accelerator Technologies, of which CLIC collaboration is a part, a 20kW Solid State RF Power Amplifier R, D & D effort by RRCAT, Indore is envisaged.
RRCAT had earlier built a 476 MHz, 10kW Solid State RF Power Amplifier for use in its FEL project which established base for the present collaboration. Long term experience in this field is available.
All required design, fabrication, testing and qualification facilities are available in-house at RRCAT.
In order to achieve the desired specifications, as well as to have feasibility studies it was thought to have 1kW, 4/5 kW intermediate stages as a part of development so that necessary improvements/ modifications can be done at 20kW level after tests at CERN.
Purushottam Shrivastava, RRCAT, CLIC Workshop Jan 26-30, 2015, CERN Geneva

3. Compact, 10kW solid state RF power MHz using LDMOS transistors and novel planar combiners and dividers for pre-buncher cavity of injector LINAC for CUTE FEL project at RRCAT
10kW SSPA during tests
A compact 10 kW, 476 MHz solid state radio frequency amplifier for pre-buncher cavity of free electron laser injector linear accelerator. Published in: Review of Scientific Instruments (Volume:84 , Issue: 9 ) Sept 2013.
Purushottam Shrivastava, RRCAT, CLIC Workshop Jan 26-30, 2015, CERN Geneva

4. Phase variation shot to shot, flat top
Specifications of the 20kW Solid State Amplifier
Parameter
Nominal value
Unit
Output power 20 kW
Frequency
499.75
MHz
Band width (3dB) 58
Pulse Length
140.3
micro sec
Repetition rate 50 Hz
Phase variation shot to shot, flat top ~1
deg
Amplitude stability %
Purushottam Shrivastava, RRCAT, CLIC Workshop Jan 26-30, 2015, CERN Geneva

5. Proposed 20kW SSPA Architecture
1:8 Wilkinson Divider
1:8 Wilkinson Combiner
Pre Driver Amplifier
I/P (Type-N)
O/P (DIN7/16)
RF Switch
Driver Amplifier x8
4kW Amplifier Modules
Purushottam Shrivastava, RRCAT, CLIC Workshop Jan 26-30, 2015, CERN Geneva

6. Feasibility Studies: Prototype development at 4/5kW power level
Generator Pre-Driver 1W Driver 100W kW
Load
5kW Prototype Amplifier Configuration
Purushottam Shrivastava, RRCAT, CLIC Workshop Jan 26-30, 2015, CERN Geneva

7. Test results of the 5kW prototype amplifier
Parameter
Test Result
Comments
Peak Power obtained
67.1dBm (~5120W)
The maximum input power required is +13dBm.
5kW
57 dB
54dB
@499.75MHz
@469.75MHz
@529.75MHz
Bandwidth (3dB)
60 MHz (+/-30MHz)
Centre Frequency MHz
Pulse To Pulse Amplitude variation
~0.1dB
@67.1dBm
Pulse to Pulse Phase variation
~1°
In pulse amplitude variation
<0.2dB
@ 67.1dBm
In pulse phase variation
<2°
5kW Amplifier Module 210mmx300mm
Amplifier Module enclosed and mounted on heat sink
Purushottam Shrivastava, RRCAT, CLIC Workshop Jan 26-30, 2015, CERN Geneva

8. Description of stages of amplifier
The amplifier has been developed as a three stage amplifier which consists of the following stages.
1 W Pre-driver amplifier
100 W GaN HEMT based driver amplifier
4kW High Power stage which is developed by combining 4 LDMOS transistors using Wilkinson combiner and divider networks on low loss flexible PTFE based laminates.
The switching ON time is defined by a RF switch which is having a controlled mono-shot circuit which sends TTL signal to switch for 150µs at rising edge of the input trigger (delay in RF ON ~200ns)
The three stages of the amplifier uses the following power supplies
1. 1W Pre-driver amplifier 24V, 600mA
2. Driver Amplifier 32V, 200mA for drain and -3.15V for Bias
3. High power stage 55V, 2A for drain and 2.15V for Bias
Input trigger signal 2.5V-5 V, 2 µs
(high Impedance)
Purushottam Shrivastava, RRCAT, CLIC Workshop Jan 26-30, 2015, CERN Geneva

9. Inside view of the amplifier system chassis.
SSPA with the DC power supply.
Back Panel has N-Type connectors for Input and Output signals, a BNC connector for Trigger Input and a 5 pin connector for D.C. Power supply connections.
Front Panel of amplifier .. The front panel contains six LED indicators, five are meant to indicate the status of Power supplies (+55V/54V, +32V,+24V,+5V,-5V) and one LED shows the trigger Input status.

10. Test Results of the prototype
Test conditions: 50Hz repetition rate, 150µs pulse width, Input Power, 12.5dBm
Output Power vs Frequency response.
Gain characteristics at Mhz
Gain characteristics at Mhz
Gain characteristics at Mhz
Purushottam Shrivastava, RRCAT, CLIC Workshop Jan 26-30, 2015, CERN Geneva

11. Amplitude and phase response of the Pulse O/P @ 499. 75MHz
Amplitude and phase response of the Pulse MHz. Left image shows the amplitude response of the amplifier as seen on a peak power analyzer. Analyzer scale 0.2dB/div. Right image shows phase detector output as seen on a CRO, Scale 10mV/div.

12. Amplifier heat sink temperature 65°C at steady state.
Conclusion:
The amplifier system was tested for all characteristics and was subjected heat run tests of more than 20 Hours, no additional cooling was required.
Amplifier power reaches thermal equilibrium after 30 minutes and has excellent phase and amplitude stability meeting specifications.
Amplifier heat sink temperature 65°C at steady state.
All the tests were performed using a 4 channel D. C. power supply which has stability of better than +/-0.05%.
For achieving the stability the 5kW amplifier module is operated at 4kW power level.
Looking into various losses and safe margin, 8 units of such modules will be integrated.
The intermediate step to build a prototype has been achieved and paves the way for the final 20kW amplifier system after further tests at CERN.
Purushottam Shrivastava, RRCAT, CLIC Workshop Jan 26-30, 2015, CERN Geneva

13. THANK YOU