2.  Combinational circuit that selects binary information from one of many input lines and directs information to a single output line.

3.  Selection inputs.  2 n input lines.  n selection inputs.  Data selector  Selects one of many inputs and steers binary information to output line.

5. ABf 00 C0 01 C1 10 C2 11 C3

6.  AND gates and inverters in multiplexer resemble a decoder circuit.  2 n - to – 1 line MUX is constructed from n-to- 2 n decoder by adding 2 n input lines.  MUX blocks can be combined in parallel with common selection & enable lines.

7.  4 multiplexers  Each capable of selecting one of two input lines. 1A  1Y 1B  Input selection line S selects one of lines in each of four MUXs.  Enable input E must be active for normal operations.

9.  Inverse of MUX  Demultiplexer receives information from a single line and transmits it to one of 2 n possible output lines.  Selection of specific output is controlled by bit combination of n selection lines.

11.  Identical to 2-to 4 line decoder with enable output. InputsEnable Decoder S1 & S0E DemultiplexerES1 & S0