1. Synchronous Sequential Circuit Design
Digital Clock Design

2. 3-bit binary ripple asynchronous counter
William Kleitz Digital Electronics with VHDL, Quartus® II Version
Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

3. The 3-bit binary ripple counter waveforms
William Kleitz Digital Electronics with VHDL, Quartus® II Version
Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

4. propagation delay on ripple counter outputs
William Kleitz Digital Electronics with VHDL, Quartus® II Version
Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

5. BCD Ripple counter

6. JKFF with falling edge trigger

7. Simulation

8. Lab. - Implement Mode 1000 counter

9. Block diagram for a digital clock
William Kleitz Digital Electronics with VHDL, Quartus® II Version
Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

10. Homework
Use synchronous sequential circuit to implement a digital clock