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2.  8051 Timers “count up,” incrementing the Timer’s respective “count register” each time there is a triggering clock pulse. 2  When the “count register” rolls over from all 1’s to all 0’s, a “Timer Flag” bit will be raised to indicate “Timer Overflow.” o Once the “Timer Flag” is set, the programmer must clear it before it can be set again (don’t forget this)  The “triggering clock pulse” that causes a timer’s count register to be incremented comes from one of two sources: o (1) The 8051’s external oscillator frequency ÷ 12 o (2) A “1  0” transition event (i.e. falling edge) on an external input (e.g. Wait_Timer0:jnb TF0,Wait_Timer0 ;wait for T0 Flag o Once a Timer overflows, the programmer must reload the initial start value to begin counting up from (don’t forget this) o Once the “Timer Flag” is set, the Timer does not stop counting, thus the programmer will usually stop the Timer to handle the event (don’t forget this)

3.  8051 has two Timers; 3 ◦ Both may be used as (1) timers or (2) event counters ◦ Both are configured by Special Function Registers  TCON (88H) – Timer CONtrol (control/status for both T1 and T0)  TMOD (89H) – Timer MODe (mode for both T1 and T0)  TH0/TL0 (8CH/8AH) – Timer 0 High/Low bytes  TH1/TL1 (8DH/8BH) – Timer 1 High/Low bytes What real-life app’s keep count?? ◦ Timer 0Timer 1 ◦ Timer 0 and Timer 1 are 16 bits wide  A timer allows program to keep track of elapsed time  A counter allows program to count external events

4.  TMOD (89H) ( Timer Mode Control Register —not bit addressable ) 4 Overflow Flag TLx(8)THx(5) Timer Clock TFx M0 TLx(8)THx(8) Timer Clock TFx M1 TLx(8) THx(8) Timer Clock TFx M2 reload TL1(8)TH1(8) Timer Clock Overflow Flag M3 TL0(8) Timer Clock TF0 TH0(8) F OSC 12 TF1 BitNameTimerComments 7Gate 1Gate Bit – Normally “0”; if “1” Timer1 only runs when INT1* = 1 3Gate 0(same) 2C/T* 0(same) 1 M1 0(same) 0 M0 0(same) 5 M1 1Timer Mode00: 13 bit timer (not used much) 4 M0 1 Select 01: 16 bit timer 10: 8 bit timer, auto-reload 11: Split mode 6C/T* 1Counter/Timer select ( 0 = Timer / 1 = Counter)

5. 5 Bit Name AddressComments 7TF1 8FhTimer1 overflow flag. Set by hardware on T1 overflow; clear by software or automatically cleared by hardware when 8051 vectors to “Timer ISR” 5 TF0 8DhTimer0 overflow flag. Set by hardware on T0 overflow; clear by software or automatically cleared by hardware when 80512 vectors to “Timer ISR” 6TR1 8EhTimer1 run-control, set/cleared by software to turn Timer1 on/off 4 TR0 8ChTimer0 run-control bit, set/cleared by software to turn Timer0 on/off 3 IE1 8BhExternal Interrupt1 edge flag. Set by hardware when a falling edge is detected on INT1* input; clear by software or automatically cleared by hardware when 8051 vectors to “Timer ISR” 2 IT1 8AhExternal Interrupt1 type control, set/cleared by software. (1=detect falling edge, 0=detect low-level) 1 IE0 89hExternal Interrupt0 edge flag 0 IT0 88hExternal Interrupt0 type control ◦ Bits 7, 5, 3 and 1 are status flags, bits 6, 4, 2 and 0 are control bits  TCON (88H) ( Timer Control Register —bit addressable ) ◦ Bits 7, 6, 3 and 2 are for using Timer1 ◦ Bits 5, 4, 1 and 0 are for using Timer0

6.  C/T* bit in TMOD controls whether it is a timer or a counter 6 In counter mode (C/T*=1) the external input (T0 or T1) is sampled in S5P2 of every machine cycle. Timer reg’s are incremented in response to 1-to-0 transition. Since it takes two machine cycles (2 us) to recognize a transition (1  0), the maximum external frequency is 500 KHz (assuming 12MHz operation). Osc. P1 P2 P1 S1 S2 S3 S4 S5 S6 S1 S2 One machine cycle F F ÷ 12 12.00 MHz crystal 1.0 MHz (1.0 uSec) 11.0592 MHz crystal 921.6 KHz (1.0851 uSec) On-chip oscillator Divide By 12 Timer Clock T0 or T1 pin C/T* P3.4 = T0 P3.5 = T1 C/T*=0 C/T*= 1 0 is up 1 is down

7.  When 8051 Timers are used in “Timer” mode, the incrementing period (T inc ) is 1/(F÷12) 7  Divide the desired delay time needed by T inc to obtain # increments (N inc ) o N inc = 50E-3 / 1E-6 = 50,000 o Example 1: if F=12 MHz then T inc = 1 µsec. o Example 2: if F=11.0592 MHz then T inc = 1.0851 µsec.  Perform 65536 - N inc (D inc )  Convert D inc to the 4-digit hexadecimal value in the form yyxx  Load TH with “yy” and TL with “xx”. TH  yy, TL  xx  Example: if F=12 MHz, find the Timer value to load to create a 50 ms delay o D inc = 65,536 – 50,000 = 15,536 o 15,536  0x3CB0; therefore yy =0x3C and xx =0xB0 o TH  0x3C; TL  0xB0

8.  What are the minimum and maximum delays that we can create ? 8 o Let’s assume the 8051 is operating at 12MHz so Timers can be incremented at 1Mhz (once every µsec). o Minimum delay is limited not by timer clock frequency but by software. Example: Write a code segment to create a waveform with the shortest possible period:  As with software delay routines, we can have 16-bit timer sections embedded in software loops to create unlimited delays clrP2.0;square wave on P2.0 Quick_Loop:cplP2.0;toggle for hi to lo sjmpQuick_Loop; and lo to hi sequence o Maximum delays using Timers are based upon the timer register size What are the Frequency and duty cycle of this waveform? o Maximum delay for 12MHz 8051 is 65536 µsec, or 65.5 msec o Maximum delay for 11.0592MHz 8051 is 65536*1.0851 µsec = 71.1 msec 8-bit timer: max count is 0 to FFh, thus max overflow occurs after 256 increments 16-bit timer: max count is 0 to FFFFh, thus max overflow occurs after 65536 increments

9. Block Diagram of Timer 1 9 and Gate = “0” When TR=1 so that Timer1 is enabled to count these signals are always “1”

10. Block Diagram of Timer 1 10 and Gate = “1” When TR=1 Timer1 only counts When INT1* = 1 this signal is only “1” when INT1* is deasserted (i.e. “1”) when INT1* goes low (i.e. asserted) Timer1 will not count this signal will be “0”

11.  Using the Gate Bit set (i.e. 1) in conjunction with inputs INTx allows the measuring of the duration of external signals (a.k.a pulse measurement) 11  In this example we measure duration of signal on INT0* ◦ Program Timer 0 to Mode 1 (16-bit timer) ◦ TH0/TL0  0000H ◦ Gate  1 ◦ TR0  1 ◦ When INT0* goes HIGH the OR-Gate is high and the count begins in 1 MHz increments (assuming 12MHz oscillator) ◦ You can program the 8051 to generate an interrupt on the HIGH to LOW transition on INT0* which tells you when to read the count ◦ When INT0* goes LOW the OR-Gate is low, counting will stop, and the count in TH0/TL0 is the number of microseconds that INT0* was asserted.

12.  This provides an 8-bit timer (Timers 0 or 1) that will automatically refresh with the initial count upon reaching the terminal count 12 TLx(8) THx(8) Timer Clock TFx Mode 2 reload  THx is programmed with the base count  TLx is the timer that will get incremented and will set the TFx bit when TLx “overflows”  When TFx bit is set, the contents of THx is automatically copied to TLx and the counting continues

13.  1 KHz Square Wave Generation 13 ORG5800H movTMOD,#00000001b;16-bit timer0 mode Loop:mov TH0, #0FEh;-500 (high byte) mov TL0, #0Ch;-500 (low byte) setbTR0;start timer Wait:jnbTF0,Wait;wait for overflow clrTR0;stop the timer clrTF0;clear timer overflow flag cplP1.0;toggle port bit sjmpLoop;repeat END ◦ Use Timer 0  Assuming 12 MHz 8051, thus 1 usec increment rate (thus T=1.0 msec = 1000 µ sec) ◦ 16-bit timer mode (delay longer than 256 µs so mode 2 can’t be used)  Duty cycle of 50%, therefore 500 µ sec low-time and 500 µ sec high-time ◦ Will need to be “tuned” if an exact output frequency is required  65536 - 500 = 65036 = 0xFE0C  Thus, TH0  0xFE and TL0  0x0C