1. FAMU-FSU College of Engineering EEL 3705 / 3705L Digital Logic Design Fall 2006 Instructor: Dr. Michael Frank Module #8: Introduction to Sequential Logic (Thanks to Dr. Perry for the slides)

2. FAMU-FSU College of Engineering Wednesday, October 25, 2006  Administrivia: This week’s lab:  Midterm practical exams Homework assignment #4:  Due tonight Midterm Exam #2:  Nov. 6 (a week from Monday) – Review on Nov. 1  Plan for today’s lecture: Start coverage of sequential logic

3. Introduction to Sequential Design

4. Types of Logic Circuits  Logic circuits can be: Combinational Logic Circuits-outputs depend only on current inputs Sequential Logic Circuits-outputs depends not only on current inputs but also on the past sequence of inputs

5. Sequential Circuit Models

6. Combinational Logic Delay Shortest delay Longest delay Longest timing delay = 5ns+5ns+5ns+5ns = 20ns Shortest timing delay = 5ns We will use the longest delay to represent the combinational logic (CL) delay, tcl

7. Combinational Logic (CL) Cloud Model Tcl=20ns

8. Memory

9.  We will add memory (or registers) to our logic circuits. This will allow us to design sequential circuits.

10. Registers  We will represent registers with the following block diagram Clock and reset are control signals Ns and ps are data signals

11. Sequential Systems Block Diagrams

12. Sequential Systems General Block Diagram Input Vector Output Vector Next State Present State Feedback Path CL= Combinational Logic Cloud Reg= D Registers Clock Reset

13. Sequential Systems General Block Diagram Input Vector Output Vector Next State Present State Feedback Path Clock Reset X is the input data vector Y is the output data vector

14. Sequential Systems Block Diagram Input Vector Output Vector Next State Present State Feedback Path Clock Reset Ns is the next state data vector Ps is the present state data vector

15. Sequential Systems Block Diagram Input Vector Output Vector Next State Present State Feedback Path Clock Reset Notice we have a feedback path which combines the ps data vector with the input vector to generate a new ns data vector.

16. Sequential Systems Block Diagram Input Vector Output Vector Next State Present State Feedback Path Clock Reset Mathematically, we say Or, ns is a function F of X and ps and Y is a function H of ps.

17. Example Circuit Schematic F LogicRegister H Logic (buffer) X input ns ps Block Diagram

18. Example Circuit Schematic F LogicRegister H Logic (buffer) X input ns ps State Equations

19. Finite State Machine (FSM) General Models

20. Moore FSM General Block Diagram Input Vector Output Vector Next State Present State Feedback Path CL= Combinational Logic Cloud Reg= D Registers Clock Reset

21. Moore FSM State Equations Input Vector Output Vector Next State Present State Feedback Path Clock Reset State Equations

22. Mealy FSM Block Diagram and State Equations Input Vector Output Vector Next State Present State Feedback Path Output Y is also a function of input X

23. Mealy-Moore FSM Block Diagram and State Equations Input Vector Next State Present State Mealy Outputs Moore Outputs

24. State Diagrams

25. State Bubble

26. State Bubble Example Unconditional Transition State name = S0 State value = 00 Y = 0 for this state Conditional Transition We leave this state if upn=1, We remain in this state if upn=0

27. Memory Devices

28.  Data Latch (D-latch)  Flip-flops (edge triggered) D-FF, D Register JK-FF T-FF

29. D-FF Positive Edge Triggered Block Diagram Symbol 4 inputs: D,Clk,Pre,Rst One output: Q D = Data Input Clk = Clock Input Pre = Preset Input Rst = Reset Input

30. D-FF Truth Table DClk dd100 dd011 d011 d111 0110 1111 Symbol Equation (rising clock) Truth Table

31. D-FF Truth Table DClk dd100 dd011 d011 d111 0110 1111 Symbol Equation (rising clock) Truth Table Pre= Preset Input (active low) Rst = Reset Input (active low) Highest priority

32. D-FF Truth Table DClk dd100 dd011 d011 d111 0110 1111 Symbol Equation (rising clock) Truth Table D = Data Input Clk = Clock input Qn = Register Output

33. FSM Examples

34. Example– 2-bit Up Counter  State Diagram Clock is implied

35. Example – 2-bit Up Counter  State Table psnsy S0S10 S21 S32 S03 S0 = 00 S1 = 01 S2 = 10 S3 = 11 Let Let S0 = reset state State Value Assignment Output Vector

36. Example – 2-bit Up Counter  Truth Table ps1ps0ns1ns0y1y0 000100 011001 101110 110011

37. Example – 2-bit Up Counter  Excitation Equations

38. Moore FSM Input Vector Output Vector Next State Present State Feedback Path Clock Reset State Equations

39. Logic Diagram F Logic H Logic Reg Block Y Vector No X Vector in this Example No H Logic needed

40. Logic Diagram

41. Flash Animation

42. Example 3– 2-bit Down Counter  State Diagram Clock is implied

43. Example – 2-bit Down Counter  State Table psnsy S0S30 S23 S12 S01 S0 = 00 S1 = 01 S2 = 10 S3 = 11 Let Let S0 = reset state

44. Example – 2-bit Down Counter  Truth Table ps1ps0ns1ns0y1y0 001100 010001 100110 111011

45. Example – 2-bit Down Counter  Excitation Equations

46. Recall Moore FSM Input Vector Output Vector Next State Present State Feedback Path Clock Reset State Equations

47. Logic Diagram F Logic H Logic Reg Block Y Vector No X Vector in this Example

48. Logic Diagram

49. Example 4 – 2-bit Up/Down Counter  State Diagram

50. Example – 2-bit Up/Down Counter  State Diagram Shorthand Notation

51. Example – 2-bit Up/Down Counter  State Table psns upn ns upn y S0S1S30 S1S2S01 S2S3S12 S3S0S23 S0 = 00 S1 = 01 S2 = 10 S3 = 11 Let Let S0 = reset state

52. Example – 2-bit Up/Down Counter  Truth Table upnps1ps0ns1ns0y1y0 0000100 0011001 0101110 0110011 1001100 1010001 1100110 1111011

53. Example – 2-bit Up/Down Counter  Excitation Equations

54. Recall Moore FSM Input Vector Output Vector Next State Present State Feedback Path Clock Reset State Equations

55. Logic Diagram X Vector Y Vector F Logic H Logic Reg Block

56. Logic Diagram

57. Example 5– 3-bit Arbitrary Counter  Design a 3-bit arbitrary counter that will count in the following sequence 3,2,3,1,2,3 If a state is not used reset it to state zero. How may states do we have? How many registers do we need? How many bits do we need for Y?

58. Example 5– 3-bit Arbitrary Counter  State Diagram

59. Example – Arbitrary 3-bit Counter  State Table psnsy S0S13 S22 S33 S41 S02 S5S00 S6S00 S7S00 S0 = 000 S1 = 001 S2 = 010 S3 = 011 S4 = 100 S5 = 101 S6 = 110 S7 = 111 Let Let S0 = reset state Assign State Values

60. Develop Truth Table

61. Example – 2-bit Arbitrary Counter  Develop Excitation Equations -- F Logic

62. Develop Excitation Equations for Y Y1 Y0

63. Example – 2-bit Arbitrary Counter  Excitation Equations -- H Logic

64. Recall Moore FSM Input Vector Output Vector Next State Present State Feedback Path Clock Reset State Equations

65. Logic Circuit F H REGREG

67. Simulation

68. FAMU-FSU College of Engineering Monday, October 30, 2006  Administrivia: This week’s lab:  Comparators and arithmetic Homework assignment #5:  Will be posted soon (if not already) Midterm Exam #2:  Nov. 6 (a week from today) – Review this Thursday  Plan for today’s lecture: Continue coverage of sequential logic

69. FAMU-FSU College of Engineering Wednesday, November 1, 2006  Administrivia: This week’s lab:  Comparators and arithmetic Homework assignment #5:  Will be posted soon (if not already) Midterm exam #2:  Postponing to Nov. 13 th – review next Wednesday  Plan for today’s lecture: Continue coverage of sequential logic

70. Example 5– 2-bit Up/Down Counter with Active Low Enable and Synchronous RESET (SRESET)  State Diagram Clock is implied

71. Example – 2-bit Up/Down Counter with Enable and SRESET  Functional Table srnenupnFunction 0dd Synchronous Reset (sreset) 11dHold 100Count Up 101Count Down Highest Level of PriorityLowest Level of Priority

72. State Table SrnEnup n ns 0ddS0 11dps 100ps+1 101ps -1

73. Truth Table (5 variables!!) Although, we could design this circuit directly from the truth table we will use design partitioning.

74. Moore FSM Architecture Input Vector Output Vector Next State Present State Feedback Path

75. Partitioned Design Note, with the partitioned design we can “reuse” already designed submodules to create the “new” design. SrnEnns 0dS0 11PS 10Count We have srn en

76. Top Level Block Diagram

77. UP/Down Logic Symbol Logic Circuit

78. Register Block Symbol Logic Circuit

79. 2 Bit 4x1 Mux Symbol Circuit

80. 1-bit 4x1 Mux Symbol Logic Circuit

81. 1-bit 2x1 Mux Symbol Logic Circuit

82. Top Level Block Diagram

83. Simulation

84. Example 6 – FSM Controller State Diagram

85. Truth Table for NS Truth Table

86. Kmaps for NS1 and NS0 NS1 NS0

87. Truth Table and Equations for Y Truth Table By Inspection Recall, Moore FSM, so Y will Not be a function of T

88. Logic Circuit F H REGREG

89. Simulation

90. Memory Devices

91. Flip-Flops

92. D-FF Truth Table Qn follows D on Rising Edge of CLK DClk dd100 dd011 d011 d111 0110 1111 Symbol Equation (rising clock) Truth Table D = Data Input Clk = Clock input Qn = Register Output

93. T-FF (Toggle) Changes state on every tick of CLK TClk Dd100 Dd011 d011 d111 011 111 Symbol Equation (rising clock) Truth Table

94. SR-FF Set =>Qn=1 Reset=>Qn=0 SRClk ddd100 ddd011 dd011 dd111 0011 01110 10111 1111??? Symbol Equation (rising clock) Truth Table

95. JK-FF JKClk ddd100 ddd011 dd011 dd111 0011 01110 10111 1111 Symbol Equation (rising clock) Truth Table

96. Example: Design a JK-FF using only Logic and a D-FF JKClk ddd100 ddd011 dd011 dd111 0011 01110 10111 1111 Symbol Truth Table

97. Example State Diagram State Table Let s0=0 and s1=1

98. JK-FF Truth TableLogic Equations

99. Recall Moore FSM State Equations Input Vector Output Vector Next State Present State Feedback Path Clock Reset State Equations

100. JK Example Circuit Schematic F LogicD-Register H Logic (buffer) X input ns ps Block Diagram

101. JK Example Circuit Schematic Simulation

102. Latches

103. D-Latch Block Diagram Symbol 4 inputs: D,E,Pre,Rst One output: Q D = Data Input E = Enable Input Pre = Preset Input Rst = Reset Input

104. D-Latch Truth Table DE dd100 dd011 d011 01110 11111 Symbol Truth Table

105. D-Latch State Equations DE dd100 dd011 d011 01110 11111 Symbol Equation (level clock) Truth Table

106. SR-Latch State Equations SR dd100 dd011 0011 01110 10111 1111??? Symbol Equation (level clock) Truth Table

107. Example T-FF D-FF D-Latch

108. Simulation

109. Modular Sequential Logic

110. Shift Registers  Logic Design which manipulates the bit position of binary data by shifting it to the left or right.  Major application Serial Data to Parallel Data converters

111. Example  Design a three-bit shift register with the following functions S1S0Function 00 Synchronous Reset (sreset) 01Shift Right 10Shift Left 11No Shift

112. Partitioned Design

113. No Shift Equations and Circuit

114. Shift Left Equations and Circuit

115. Shift Right Equations and Circuit

116. Synchronous Reset Module

117. Registers

118. Total Design