1. Fabrication of MOSFETs
Introduction and Fabrication Procedure
Amit Degada
Asst. Professor

2. Introduction Integrated circuits: many transistors on one chip.
Very Large Scale Integration (VLSI): millions of logic gates + many Mbits of memroy
Complementary Metal Oxide Semiconductor
Fast, cheap, low power transistors
Today: How to build your own simple CMOS chip
CMOS transistors
Building logic gates from transistors
Transistor layout
Rest of the course: How to build a good CMOS chip

3. A Brief History 1958: First integrated circuit 2003
Built by Jack Kilby at Texas Instruments with 2 transistors
2003
Intel Pentium 4 mprocessor (55 million transistors)
512 Mbit DRAM (> 0.5 billion transistors)
53% compound annual growth rate over 45 years
No other technology has grown so fast so long
Driven by miniaturization of transistors
Smaller is cheaper, faster, lower in power!
Revolutionary effects on society

4. Annual Sales 1018 transistors manufactured in 2003
100 million for every human on the planet
$100B business in 2004

5. Invention of the Transistor
Vacuum tubes ruled in first half of 20th century Large, expensive, power-hungry, unreliable
1947: first point contact transistor
John Bardeen and Walter Brattain at Bell Labs

6. Transistor Types Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls large currents between emitter and collector
Base currents limit integration density (power dissipation issue)
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current between source and drain
Low power allows very high integration (ideally zero static power)

7. MOS Integrated Circuits
1970’s processes usually had only nMOS transistors
Inexpensive, but consume power while idle
1980s-present: CMOS processes for low idle power
Intel bit SRAM
Intel bit mProc

8. Moore’s Law 1965: Gordon Moore plotted transistor on each chip
Fit straight line on semilog scale
Transistor counts have doubled every 18 months
Integration Levels
SSI: 10 gates
MSI: gates
LSI: 10,000 gates
VLSI: > 10k gates

9. Corollaries Many other factors grow exponentially
Ex: clock frequency, processor performance

10. Silicon Lattice Transistors are built on a silicon substrate
Silicon is a Group IV material
Forms crystal lattice with bonds to four neighbors

11. Dopants Silicon is a semiconductor
Pure silicon has no free carriers and conducts poorly
Adding dopants increases the conductivity
Group V (Arsenic): extra electron (n-type)
Group III (Boron): missing electron, called hole (p-type)

12. p-n Junctions
A junction between p-type and n-type semiconductor forms a diode.
Current flows only in one direction

13. nMOS Transistor Four terminals: gate, source, drain, body
Gate – oxide – body stack looks like a capacitor
Gate and body are conductors
SiO2 (oxide) is a very good insulator
Called metal – oxide – semiconductor (MOS) capacitor

14. nMOS Operation Body is commonly tied to ground (0 V)
When the gate is at a low voltage:
P-type body is at low voltage
Source-body and drain-body diodes are OFF
No current flows, transistor is OFF

15. nMOS Operation Cont. When the gate is at a high voltage:
Positive charge on gate of MOS capacitor
Negative charge attracted to body
Inverts a channel under gate to n-type
Now current can flow through n-type silicon from source through channel to drain, transistor is ON
0: Introduction

16. pMOS Transistor Similar, but doping and voltages reversed
Body tied to high voltage (VDD)
Gate low: transistor ON
Gate high: transistor OFF
Bubble indicates inverted behavior

17. Power Supply Voltage GND = 0 V In 1980’s, VDD = 5V
VDD has decreased in modern processes due to scaling
High VDD would damage modern tiny transistors
Lower VDD saves power (Dynamic power is propotional to C.VDD2.f.a)
VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …

18. Transistors as Switches
We can view MOS transistors as electrically controlled switches
Voltage at gate controls path from source to drain

19. CMOS Inverter A Y 1

20. CMOS Inverter A Y 1

21. CMOS Inverter A Y 1

22. CMOS NAND Gate A B Y 1

23. CMOS NAND Gate A B Y 1

24. CMOS NAND Gate A B Y 1
0: Introduction

25. CMOS NAND Gate A B Y 1

26. Introduction and Fabrication Procedure

27. Objective of the Lecture
Design of Logics in CMOS
Why to Study Fabrication?
Flow Diagram.
Fabrication Process Flow:Basic Steps

28. CMOS NOR Gate A B Y 1

29. 3-input NAND Gate Y pulls low if ALL inputs are 1
Y pulls high if ANY input is 0

30. 3-input NAND Gate Y pulls low if ALL inputs are 1
Y pulls high if ANY input is 0

31. Complementary CMOS Complementary CMOS logic gates
nMOS pull-down network
pMOS pull-up network
a.k.a. static CMOS
Pull-up OFF
Pull-up ON
Pull-down OFF
Z (float) 1
Pull-down ON
X (crowbar)

32. Series and Parallel nMOS: 1 = ON pMOS: 0 = ON Series: both must be ON
Parallel: either can be ON

33. Conduction Complement
Complementary CMOS gates always produce 0 or 1
Ex: NAND gate
Series nMOS: Y=0 when both inputs are 1
Thus Y=1 when either input is 0
Requires parallel pMOS
Rule of Conduction Complements
Pull-up network is complement of pull-down
Parallel -> series, series -> parallel

34. Compound Gates
Compound gates can do any inverting function
Ex:

35. Example: O3AI

36. Example: O3AI

37. Objective of the Lecture
Design of Logics in CMOS
Why to Study Fabrication?
Flow Diagram.
Fabrication Process Flow:Basic Steps

38. Why to study Fabrication?
Strong link between Fabrication Process , the circuit design procedure and the performance of resulting chip
The circuit designer must have clear understanding of the roles of various MASKs used in the fabrication procedure and How this MASKs define various feature of the devices on a Chip
To know to create effective design.
To optimize the circuit with respect to various manufacturing parameters.

39. Well Requires to build both pMOS and nMOS on single wafer.
To accommodate both pMOS and nMOS devices, special regions must be created in which the semiconductor type is oppossite of the substrate type.
Also Known as Tubs.
Twin-tubs

40. Objective of the Lecture
Design of Logics in CMOS
Why to Study Fabrication?
Flow Diagram.
Fabrication Process Flow:Basic Steps

41. Flow Diagram Create n-Well regions and Channel Stops region
Grow Field Oxide and
Gate Oxide
Deposite and pattern
Polysilcon Layer
Implant sources, drain regions and substrate contacts
Create contact Windows, deposit and pattern metal layer

42. Objective of the Lecture
Design of Logics in CMOS
Why to Study Fabrication?
Flow Diagram.
Fabrication Process Flow:Basic Steps

43. Fabrication Procedure Flow: Basic Steps
Masks: Each Processing steps in the fabrication procedure requires to define certain area on the chip. This is known as Masks.
Chips are specified with set of masks
Minimum dimensions of masks determine transistor size (and hence speed, cost, and power)
Feature size f = distance between source and drain
Set by minimum width of polysilicon
Feature size improves 30% every 3 years or so
Normalize for feature size when describing design rules
The ICs are viewed as a set of pattern layers of doped Silicon, Polysilicon, Metal and Insulating Silicon Dioxide.
A layer mut be Patterned before the next layer of material is applied on the chip.

44. Inverter Cross-section
Typically use p-type substrate for nMOS transistors
Requires n-well for body of pMOS transistors

45. Inverter Cross-section with Well and Substrate taps
Typically use p-type substrate for nMOS transistors
Requires n-well for body of pMOS transistors
Substrate must be tied to GND and n-well to VDD
Metal to lightly-doped semiconductor forms poor connection
Use heavily doped well and substrate contacts / taps

46. Inverter Mask Set Transistors and wires are defined by masks
Cross-section taken along dashed line

47. Detailed Mask Views Six masks n-well Polysilicon n+ diffusion
p+ diffusion
Contact
Metal

48. Pattern Preparation
Chrome Pattern
Quartz Substrate
Pellicle

49. Wafer Preparation

50. Wafer Preparation

51. Fabrication Steps Start with blank wafer
Build inverter from the bottom up
First step will be to form the n-well
Cover wafer with protective layer of SiO2 (oxide)
Remove layer where n-well should be built
Implant or diffuse n dopants into exposed wafer
Strip off SiO2

52. Oxidation Grow SiO2 on top of Si wafer
900 – 1200 C with H2O or O2 in oxidation furnace

53. Photolithography
Exposure Processes

54. Photoresist Used for lithography .
Lithography is a process used to transfer a pattern to layer on the chip. Similar to Printng Process
Spin on photoresist (about 1 mm thickness)
Photoresist is a light-sensitive organic polymer
Possitive Photoresist: Softens where exposed to light
Negative Photresist: Harden where exposed to light, Not used in practise generally

55. Lithography Expose photoresist through n-well mask
Strip off exposed photoresist

56. Etch Die-electric Etch Plasma Etch Cluster Tool Etch Configuration
Chambers
Cluster Tool
Configuration
Transfer
Chamber
Loadlock
Wafers
RIE Chamber
Transfer
Chamber
Gas Inlet
Exhaust
RF Power
Wafer
Die-electric Etch
Plasma Etch

57. Etch Etch oxide with hydrofluoric acid (HF)
Seeps through skin and eats bone; nasty stuff!!!
Only attacks oxide where resist has been exposed

58. Strip Photoresist Strip off remaining photoresist
Use mixture of acids called piranah etch
Necessary so resist doesn’t melt in next step

59. n-well n-well is formed with diffusion or ion implantation Diffusion
Place wafer in furnace with arsenic gas
Heat until As atoms diffuse into exposed Si
Ion Implanatation
Blast wafer with beam of As ions
Ions blocked by SiO2, only enter exposed Si

60. Ion Implantation Focus Neutral beam and beam path gated Beam trap and
gate plate
Wafer in wafer
process chamber
X - axis
scanner
Y - axis
Neutral beam trap
and beam gate

61. Strip Oxide Strip off the remaining oxide using HF
Back to bare wafer with n-well
Subsequent steps involve similar series of steps

62. Polysilicon Deposit very thin layer of gate oxide
< 20 Å (6-7 atomic layers)
Chemical Vapor Deposition (CVD) of silicon layer
Place wafer in furnace with Silane gas (SiH4)
Forms many small crystals called polysilicon
Heavily doped to be good conductor

63. Polysilicon Patterning
Use same lithography process to pattern polysilicon

64. Self-Aligned Process
Use oxide and masking to expose where n+ dopants should be diffused or implanted
N-diffusion forms nMOS source, drain, and n-well contact

65. N-diffusion Pattern oxide and form n+ regions
Self-aligned process where gate blocks diffusion
Polysilicon is better than metal for self-aligned gates because it doesn’t melt during later processing

66. N-diffusion cont. Historically dopants were diffused
Usually ion implantation today
But regions are still called diffusion

67. N-diffusion cont.
Strip off oxide to complete patterning step

68. P-Diffusion
Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact

69. Contacts
Now we need to wire together the devices
Cover chip with thick field oxide
Etch oxide where contact cuts are needed

70. Metalization Sputter on aluminum over whole wafer
Pattern to remove excess metal, leaving wires

71. Testing
Defective IC
Individual integrated circuits are tested to distinguish good die from bad ones.

72. Die Cut and Assembly Good chips are attached to a lead frame package.
After electrical test, the wafer is scored with a special diamond saw and broken into individual die. The marked (non-functional) die are discarded and functional die are passed on into the wire bonding process.
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73. Die Attach and Wire Bonding
lead frame
gold wire
bonding pad
Die Attach and Wire Bonding
Once separated into individual die, the functional devices are attached to a lead frame assembly. A drop of precisely engineered compound is placed beneath the die to glue it to the lead frame assembly and provide good electrical grounding and heat transfer for the silicon device.
Aluminum or gold leads are attached via thermal compression or ultrasonic welding. The automated process attaches the ultra-thin wires (about 30 µm in diameter, 1/3 the diameter of a human hair) between each device bonding pad and a connector of the lead frame.
There are thousands of different packages available, each specially engineered to provide a specific benefit such as small package size, high frequency information transmission or protection from extreme environmental conditions such as heat, cold or moisture.
connecting pin
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74. Final Test
Chips are electrically tested under varying environmental conditions.
Final Test
After wire bonding is completed, the packaging is completed by molding the device into a plastic enclosure.
Packages are precisely engineered to provide good thermal conductivity, easy assembly into printed circuit boards and protection from damaging environmental conditions.
These packages are often tested again and sorted by performance speed because faster chips sell for higher margins than slower chips. Some chips receive special testing by being place in high temperature ovens or in warm, humid environments or are subject to repeated cycling between extreme hot and cold temperatures. These tests help engineers ensure that the product reliability is within specified limits.
After final testing, the chips are packed into shipping containers and shipped to customers.
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75. Device Isolation Techniques
The MOS transistors need to be electrically isolated during fabrication.
Isolation is necessary to prevent unwanted conduction paths between devices and to avoid creation of inversion layer outside channel sepration region and to reduce leackage currents
Active area is created, which is surronded by a relatively thick oxide barrier called the field oxide.
Ethced field oxide isolation. ( Grow Silicon Oxide and Etched away u
Necessary).
Disadvantage: Thickness of the field oxide leads to large Oxide steps at the boundry of Active and isolated regions.
This leads to the cracking of layer (Hence Chip Failure) when metal/ Poly is deposited in next steps
Final Test
After wire bonding is completed, the packaging is completed by molding the device into a plastic enclosure.
Packages are precisely engineered to provide good thermal conductivity, easy assembly into printed circuit boards and protection from damaging environmental conditions.
These packages are often tested again and sorted by performance speed because faster chips sell for higher margins than slower chips. Some chips receive special testing by being place in high temperature ovens or in warm, humid environments or are subject to repeated cycling between extreme hot and cold temperatures. These tests help engineers ensure that the product reliability is within specified limits.
After final testing, the chips are packed into shipping containers and shipped to customers.
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76. Local Oxidation of Silicon (LOCOS)
Final Test
After wire bonding is completed, the packaging is completed by molding the device into a plastic enclosure.
Packages are precisely engineered to provide good thermal conductivity, easy assembly into printed circuit boards and protection from damaging environmental conditions.
These packages are often tested again and sorted by performance speed because faster chips sell for higher margins than slower chips. Some chips receive special testing by being place in high temperature ovens or in warm, humid environments or are subject to repeated cycling between extreme hot and cold temperatures. These tests help engineers ensure that the product reliability is within specified limits.
After final testing, the chips are packed into shipping containers and shipped to customers.
Based on the Principal of selectively Growing the oxide rahter than etching.
Selectice Growth is achieved by shielding the Active area with Silicon Nitride (Si3N4)
First Thin oxide is grown followed by deposition and patterning of Silicon Nitride (Si3N4)
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77. Local Oxidation of Silicon (LOCOS)
Final Test
After wire bonding is completed, the packaging is completed by molding the device into a plastic enclosure.
Packages are precisely engineered to provide good thermal conductivity, easy assembly into printed circuit boards and protection from damaging environmental conditions.
These packages are often tested again and sorted by performance speed because faster chips sell for higher margins than slower chips. Some chips receive special testing by being place in high temperature ovens or in warm, humid environments or are subject to repeated cycling between extreme hot and cold temperatures. These tests help engineers ensure that the product reliability is within specified limits.
After final testing, the chips are packed into shipping containers and shipped to customers.
Exposed area form the isolation region and doped with P Kind of impurities P
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78. Local Oxidation of Silicon (LOCOS)
Final Test
After wire bonding is completed, the packaging is completed by molding the device into a plastic enclosure.
Packages are precisely engineered to provide good thermal conductivity, easy assembly into printed circuit boards and protection from damaging environmental conditions.
These packages are often tested again and sorted by performance speed because faster chips sell for higher margins than slower chips. Some chips receive special testing by being place in high temperature ovens or in warm, humid environments or are subject to repeated cycling between extreme hot and cold temperatures. These tests help engineers ensure that the product reliability is within specified limits.
After final testing, the chips are packed into shipping containers and shipped to customers.
Thick oxide is grown in next step where the area is not covered by Si3N4.
Birds Beak Region.
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79. Local Oxidation of Silicon (LOCOS)
Final Test
After wire bonding is completed, the packaging is completed by molding the device into a plastic enclosure.
Packages are precisely engineered to provide good thermal conductivity, easy assembly into printed circuit boards and protection from damaging environmental conditions.
These packages are often tested again and sorted by performance speed because faster chips sell for higher margins than slower chips. Some chips receive special testing by being place in high temperature ovens or in warm, humid environments or are subject to repeated cycling between extreme hot and cold temperatures. These tests help engineers ensure that the product reliability is within specified limits.
After final testing, the chips are packed into shipping containers and shipped to customers.
Etching of Si3N4 and thin Oxide.
Most Popular Techniques.
Later Some techniques are developed to control Bird’s Beak Region.
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80. Summary MOS Transistors are stack of gate, oxide, silicon
Can be viewed as electrically controlled switches
Build logic gates out of switches
Draw masks to specify layout of transistors
Now you know everything necessary to start designing schematics and layout for a simple chip!

81. References
1. CMOS Process Flow in Wafer Fab, Semiconductor Manufacturing Technology, DRAFT, Austin Community College, January 2, 1997.
2. Semiconductor Processing with MKS Instruments, Inc.
3. Worthington, Eric. “New CMP architecture addresses key process issues,” Solid State Technology, January 1996.
4. Leskonic, Sharon. “Overview of CMP Processing,” SEMATECH Presentation, 1996.
5. Gwozdz, Peter. “Semiconductor Processing Technology” SEMI, 1997.
6. CVD Tungsten, Novellus Sales Brochure, 7/96.
7. Fullman Company website. “Fullman Company - The Semiconductor Manufacturing Process,”
8. Barrett, Craig R. “From Sand to Silicon: Manufacturing an Integrated Circuit,” Scientific American Special Issue: The Solid State Century, January 22, 1998.
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82. Thanks Give Your Feedbacks at: www.amitdegada.weebly.com/blog.html
References
I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments.
For further reading, I especially recommend the reference from Scientific American.
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