1. Power Distribution Studies at Fermilab Aida Todri, FNAL ATLAS/CMS Power WG Meeting March 31 st, 2010

2. Outline  Panel test stand.  System setup.  DC-DC conversion powering scheme tests:  Efficiency measurements.  Cooling impact on converter.  Pixel performance measurements. 2

3. Panel Test Stand 3  CAPTAN  DAQ system, 12bit ADC, 65MHz  Panel  21 ROCs, TBM, 40MHz, Ianalog~1.35A, Idigital~1.5A with external load  Converters  AMIS2 DC-DC converters for V A and V D.

4. Pixel Calibration 4 Analog signal in ADC counts from all the readout chips in a panel sampled by the front-end digitizer. Decoding of analog signal.

5. DC-DC Converters 5  Chip: AMIS2 by CERN  Vin=6-12V  Iout<3A  Vout=3.3V  fs=600kHz..3MHz  PCB: Aachen  2 copper layers  External air-core inductor  L=550nH, R=80m Ω AMIS2

6. Efficiency Measurements (w/o cooling) 6 DIGITAL TempVinInVoutIoutEff room = 28 ˚ C 80.7983.3271.49277.76% 8.50.7553.3271.49277.35% 90.7163.3311.49477.23% 9.50.6853.3411.48876.40% 100.6563.3471.576.53% 10.50.6323.3551.50375.99% 110.6083.3621.50575.66% 11.50.593.3721.51375.19% 120.5713.381.50774.34% ANALOG TempVinInVoutIoutEff room = 28 ˚ C 80.7253.351.3779.13% 8.50.693.361.3778.49% 90.6573.361.3777.85% 9.50.633.371.3877.70% 100.6083.381.3876.72% 10.50.5833.381.3876.20% 110.5693.41.476.05% 11.50.5493.41.475.39% 120.5333.411.474.64%

7. Impact of Chip Cooling 7  Observation : Cooling the converter chip ~20 ˚ C impacts the regulator and decreases the voltage level being supplied to the panel.  Cause degradation in the signal pulse. w/ coolingno cooling

8. Temperature Measurement 8 T on_chip =70 ˚ C T on_ind =88 ˚ C T on_chip =69 ˚ C T on_ind =106.8 ˚ C no coolingwith air fan cooling

9. Efficiency w/ Cooling 9

10. Power Supply Noise No converter w/ DC-DC converters 10 Vout=3.26V, Vin=9V Temp=62.8 ˚ C Vout=2.42V ∆ =278mV

11. Performance Measurements S-Curve Test: 11  To measure the signal threshold and noise level of each pixel.  Efficiency of the pixel is derived as a function of the amplitude of the calibration signal.  Each pixel response is obtained by injecting calibration pulses with different Vcal DAC values (1Vcal=65e).  S-Curve calibration is run with and without DC-DC converters.

12. Noise and Threshold Dispersion 12

13. Pixel Noise Maps 13

14. Threshold Dispersion Maps 14

15. Serial Powering Test Stand  SPi Chip: FNAL  V shunt =1.2 to 3V  I series =0 to 4A 15  CAPTAN sending data packets to program the SPi chip to operate at different modes.  SPi powered through a power supply source by limiting current.  Limited current output to drive a plaquette or panel  Used ~ 250mA

16. Next Test Setup 16 CAEN A4603 DC-DC Conversion Panel  Setup modified CAEN A4603 module to power up the chips  Perform test a lower temperatures (chiller box)  Perform test with a magnet 1.5T.

17. Conclusions  Currently:  Performing power integrity tests on the panel system  Performing pixel performance measurements  Characterizing the DC-DC converter and serial powering schemes and their efficiencies  Next Steps:  Continue with performance measurement studies for DC-DC powering scheme.  Complete test stand setup using:  CAEN power supply, magnet, cooler temps.  Testing of serial powering scheme  Efficiency comparisons between two schemes. 17