2. MIGRATING FROM SDRAM TO DDR Bill Gervasi Vice Chairman, JEDEC Memory Timing Technology Analyst bilge@transmeta.com

3. 2 Topics to Cover About JEDEC & DDR About JEDEC & DDR Market Segments & Fragments Market Segments & Fragments Design Architectures Design Architectures DDR Solutions DDR Solutions Changes from SDR to DDR Changes from SDR to DDR Timing Diagrams Timing Diagrams Impact to board design Impact to board design Why Not Rambus? Why Not Rambus?

4. 3 About JEDEC & DDR Setting open standards for >25 years Setting open standards for >25 years Consortium of 350 companies Consortium of 350 companies  Memory suppliers  Users from all market segments Double Data Rate (DDR) SDRAM Double Data Rate (DDR) SDRAM  Latest approved JEDEC standard  Results of collaborative market analysis

5. 4 Segments & Fragments Servers Workstations PC Segment 2 PC Segment 1 PC Segment 0 Mobile Graphics 2H991H002H001H01 PC100 DDR PC100 DDR PC100 Rambus DDR PC100 PC66 PC100 DDR PC133 SS167 DDR SDRAM (x16) DDR 2H01 Rambus DDR PC133 DDR SDRAM(x32)

6. 5 Market Factors Server per-system memory capacity increasing faster than PC Server per-system memory capacity increasing faster than PC Segments 1, 2 split Intel & non-Intel Segments 1, 2 split Intel & non-Intel UMA graphics takes over Segs 0 & 1 UMA graphics takes over Segs 0 & 1  “Sealed Box” PC for home market Mobile market mostly skips PC-133 Mobile market mostly skips PC-133  DDR power lower than SDR Graphics early: short design cycles Graphics early: short design cycles

7. 6 RAM Evolution 320MB/s 400MB/s 1000MB/s 2100MB/s Mainstream Memories FP EDO SDR DDR Simple, incremental steps DDR II 3200MB/s

8. 7 Continued Tradition DDR is the logical incremental step Performance enhancements Performance enhancements Detailed documentation Detailed documentation Full support from vendors & users Full support from vendors & users

9. 8 System Designs Sockets & Stubs Sockets & Stubs 133MHz clock 133MHz clock 2.1GB/s transfer 2.1GB/s transfer Point to point Point to point 200MHz clock 200MHz clock 3.2GB/s transfer 3.2GB/s transfer Small Systems Controller PC/Server Memory Controller* * Single chip or separate clock, data & address chips

10. 9 DDR Solutions PC-266 Devices PC-2100 Modules 1-4 Slots Long traces, < 8” Termination No dummy modules SS-400 Devices Direct connect 2-8 DDR SDRAMs Short traces, < 2” No termination Built for speed PC/Server Applications Small Systems

11. 10 How Different is DDR? Simple upgrade to SDR designs Simple upgrade to SDR designs  Similar PCB characteristics  Same fast RAS/CAS command set A few evolutionary improvements A few evolutionary improvements  Bidirectional data strobe  Low voltage swing I/O JEDEC Standards JEDEC Standards  Data sheet including IBIS curves  Module gerbers, application notes

12. 11 From SDR to DDR Signaling Clocks Data Strobe Packages Pin Count

13. 12 From SDR to DDR Signaling Clocks Data Strobe Packages Pin Count

14. 13 DDR Signaling SSTL_2 low voltage swing inputs SSTL_2 low voltage swing inputs  2.5V I/O with 1.25V reference voltage  Low voltage swing with termination  Rail to rail if unterminated

15. 14 From SDR to DDR Signaling Clocks Data Strobe Packages Pin Count

16. 15 DDR Clocks Differential clocks on adjacent traces Differential clocks on adjacent traces Timing is relative to crosspoint Timing is relative to crosspoint Helps insure 50% duty cycle Helps insure 50% duty cycle

17. 16 “Slow” Signal Timing Based on CK  Based on CK  Loading mismatch,  single data rate Loading mismatch,  single data rate Addresses & Control signals Addresses & Control signals

18. 17 From SDR to DDR Signaling Clocks Data Strobe Packages Pin Count

19. 18 “Fast” DDR Read Timing Data valid on rising & falling edges Data valid on rising & falling edges Source Synchronous: Source Synchronous:  Data Strobe “DQS” travels with data

20. 19 Read Timing 200MHz CK t DV insures worst case shift on DQS can’t happen (sufficient timing margin for system design!)

21. 20 A Totally Sync Design Operate solely in memory clock timing domain Operate solely in memory clock timing domain Fast design for small systems Fast design for small systems  Tight layout required

22. 21 “Fast” DDR Write Timing DQS centered in data valid eye DQS centered in data valid eye DM timing & loading identical to DQ DM timing & loading identical to DQ Flexible to support large systems Flexible to support large systems

23. 22 DDR Write Design Hint “Perfect” alignment at 1.0 * tCK Good solution for single chip controllers Early DQS stresses back to back ops Early DQS stresses back to back ops Late stresses the array update Late stresses the array update  1.0 * t CK is best  1.0 * t CK is best

24. 23 Emphasis on “Matched” DM/DQS loading identical to DQ DM/DQS loading identical to DQ Route as independent 8bit buses Route as independent 8bit buses DQ/DQS DM V REF Disable CONTROLLERDDR SDRAM

25. 24 64 = 8 x 8 64bit bus is 8 sync’ed 8bit buses 64bit bus is 8 sync’ed 8bit buses Allows external “copper” flexibility Allows external “copper” flexibility 8 buses resync upon entry to FIFO 8 buses resync upon entry to FIFO 8 DQ 1 DM 1 DQS 8bit Buffer 8 DQ 1 DM 1 DQS x16 DDR SDRAM 64bit Memory Controller Internal FIFO Sync to Controller clock Copper from controller to SDRAMs Inside Controller x16 DDR SDRAM 8 DQ 1 DM 1 DQS

26. 25 From SDR to DDR Signaling Clocks Data Strobe Pin Count Packages

27. 26Packages Device Device  66pin TSOP same size as 54pin TSOP  Same 400x875mil,.65mm vs.80mm DIMM DIMM  184pin same size as 168pin  Same 5.25”, same pin pitch (key filled) SO-DIMM SO-DIMM  200pin slightly longer than 144pin  73mm vs. 68mm,.65mm vs..80mm

28. 27 From SDR to DDR Signaling Clocks Data Strobe Packages Pin Count

29. 28 Pin Count Versus SDR One DQS for 8 DQ (x8, x16 SD) --- or --- One DQS for 8 DQ (x8, x16 SD) --- or --- One DQS for every 32 DQ (x32 SG) One DQS for every 32 DQ (x32 SG) One /CK adjacent to every CK One /CK adjacent to every CK One V REF One V REF Additional V DD Q, V SS ? Additional V DD Q, V SS ?  DQ/DM/DQS:V DD Q:V SS ratio of 4:1:1 Total: 5-12 more pins Total: 5-12 more pins

30. 29 Combined SDR/DDR SDR 3.3V I/O supply 3.3V I/O supply Single ended CLK Single ended CLK Echo CLK for reads Echo CLK for reads No write latency No write latency CAS latency 2, 3 CAS latency 2, 3 Series termination Series termination Burst length 1, 2, 4, 8 Burst length 1, 2, 4, 8 No reference voltage No reference voltageDDR 2.5V I/O supply 2.5V I/O supply Differential CK and CK Differential CK and CK DQS for reads DQS for reads Write latency one clock Write latency one clock CAS latency 2, 2.5, (3) CAS latency 2, 2.5, (3) Series & parallel term’n Series & parallel term’n Burst length 2, 4, 8 Burst length 2, 4, 8 Reference voltage V REF Reference voltage V REF Combined SDR & DDR controller is a reasonable way to minimize risks Combined SDR & DDR controller is a reasonable way to minimize risks

31. 30 Hints for the Future You’ll get the fastest designs if you: Don’t use command interrupts Don’t use command interrupts Don’t use autoprecharge Don’t use autoprecharge Fixed burst length 4 Fixed burst length 4 Programmable drive impedance Programmable drive impedance  Weak and strong drivers are standard Unbroken ground planes & islands Unbroken ground planes & islands

32. 31 Why Not Rambus?

33. 32 Compare DDR & Rambus

34. 33 DDR Versus Rambus DDR Advantage $10 + royalties $10 + royalties 15% 15% 27% 27% 33% 33% 40% 40%Reason Die, Heat sinks, dummy modules Die, Heat sinks, dummy modules 28  ±10% vs. 55  ±15% 28  ±10% vs. 55  ±15% Packet protocol Packet protocol Frequency * width Frequency * width Frequency Frequency DIMM cost: PCB cost: Latency: Peak BW: Power: Email me to get the white paper detailing this analysis

35. 34 Rambus Market Issues High latency High latency  Poor fit for UMA graphics High power High power  Poor fit for mobile Costly materials Costly materials  Poor fit for cost sensitive systems Leaves the $2500+ PC market as a fit Leaves the $2500+ PC market as a fit  Insufficient volumes to create a market  Other solutions needed anyway

36. 35Summary DDR is here today DDR is here today  Double the bandwidth  Evolutionary design change over SDR  Cheaper, faster, & cooler than Rambus  Applies to all market segments Industry Standards Industry Standards  Detailed complete data sheet & models  Module designs on the web  Visit http://www.jedec.org

37. 36 Call to Action Watch all the market trends Watch all the market trends Let your memory vendor know about your commitment to DDR Let your memory vendor know about your commitment to DDR Let the trade press know your choice Let the trade press know your choice Use smart engineering to push limits Use smart engineering to push limits Join JEDEC and influence the future Join JEDEC and influence the future

38. 37 Thank You