1. CS1104: Computer Organisation http://www.comp.nus.edu.sg/~cs1104 Lecture 6: Combinational Circuits Design Methods/Arithmetic Circuits http://www.comp.nus.edu.sg/~cs1104

2. CS1104-6L ecture 6:Combinational Circuits: Design Methods/Arithmetic Circuits 2  Introduction Introduction  Analysis Procedure Analysis Procedure  Design Methods Design Methods  Gate-level (SSI) Design Gate-level (SSI) Design  Half Adder Half Adder  Full Adder Full Adder  BCD-to-Excess-3 Code Converter BCD-to-Excess-3 Code Converter  Block-Level Design Block-Level Design  4-bit Parallel Adder 4-bit Parallel Adder  BCD-to-Excess-3 Code Converter BCD-to-Excess-3 Code Converter  16-bit Parallel Adder 16-bit Parallel Adder  4-bit Parallel Adder cum Subtractor 4-bit Parallel Adder cum Subtractor

3. CS1104-6Lecture 6: Combinational Circuits: Design Methods/Arithmetic Circuits 3  Arithmetic Circuits Arithmetic Circuits  Adders Adders  Parallel Adders Parallel Adders  Cascading Adders Cascading Adders  Parallel Adder-Subtractor Parallel Adder-Subtractor  Comparator Comparator  Calculations of Circuit Delays Calculations of Circuit Delays  Faster Circuits Faster Circuits  Look-Ahead Carry Adder Look-Ahead Carry Adder

4. CS1104-6Introduction4 Introduction (1/2)  Two classes of logic circuits:  combinational  sequential  Combinational Circuit: Each output depends entirely on the immediate (present) inputs. Combinational Logic : inputsoutputs

5. CS1104-6Introduction5 Introduction (2/2)  Sequential Circuit: (not covered) Output depends on both present and past inputs. Memory (via feedback loop) contains past information. Combinational Logic : inputsoutputs : Memory

6. CS1104-6Analysis Procedure6  Given a combinational circuit, can you analyze its function?  Steps:  1. Label the inputs and outputs. ABAB F1 F2 A+B A'+B' = (A+B).(A'+B') = (A'+B')' = A.B  2. Obtain the functions of intermediate points and the outputs.  3. Draw the truth table.  4. Deduce the functionality of the circuit  half adder.

7. CS1104-6Design Methods7 Design Methods (1/2)  Different combinational circuit design methods:  Gate-level method (with logic gates)  Block-level design method  Design methods make use of logic gates and useful functional blocks.  These are available as Integrated Circuit (IC) chips.

8. CS1104-6Design Methods8 Design Methods (2/2)  Type of IC chips (based on packing density) :  Small-scale integration (SSI): up to 12 gates  Medium-scale integration (MSI): 12-99 gates  Large-scale integration (LSI): 100-9999 gates  Very large-scale integration (VLSI): 10,000-99,999 gates  Ultra large-scale integration (ULSI): > 100,000 gates  Main objectives of circuit design:  (i) reduce cost  reduce number of gates (for SSI circuits)  reduce IC packages (for complex circuits)  (ii) increase speed  (iii) design simplicity (reuse blocks where possible)

9. CS1104-6Gate-level (SSI) Design: Half Adder 9 Gate-level (SSI) Design: Half Adder (1/2)  Design procedure: 1) State Problem Example: Build a Half Adder to add two bits 2) Determine and label the inputs & outputs of circuit. Example: Two inputs and two outputs labelled, as follows: Half Adder XYXY SCSC (X + Y) 3) Draw truth table.

10. CS1104-6Gate-level (SSI) Design: Half Adder 10 Gate-level (SSI) Design: Half Adder (2/2) 4) Obtain simplified Boolean function. Example: C = X.Y S = X'.Y + X.Y' = X  Y XYXY S C Half Adder 5) Draw logic diagram.

11. CS1104-6Gate-level (SSI) Design: Full Adder 11 Gate-level (SSI) Design: Full Adder (1/5)  Half-adder adds up only two bits.  To add two binary numbers, we need to add 3 bits (including the carry).  Example:  Need Full Adder (so called as it can be made from two half-adders). Full Adder XYZXYZ SCSC (X + Y + Z)

12. CS1104-6Gate-level (SSI) Design: Full Adder 12 Gate-level (SSI) Design: Full Adder (2/5)  Truth table: Note: Z - carry in (to the current position) C - carry out (to the next position)  Using K-map, simplified SOP form: C = X.Y + X.Z + Y.Z S = X'.Y'.Z + X'.Y.Z'+X.Y'.Z'+X.Y.Z 0 10 1 00 01 11 10 X YZ 111 1 C 0 10 1 00 01 11 10 X YZ 11 11 S

13. CS1104-6Gate-level (SSI) Design: Full Adder 13 Gate-level (SSI) Design: Full Adder (3/5)  Alternative formulae using algebraic manipulation: C = X.Y + X.Z + Y.Z = X.Y + (X + Y).Z = X.Y + ((X  Y) + X.Y).Z = X.Y + (X  Y).Z + X.Y.Z = X.Y + (X  Y).Z S = X'.Y'.Z + X'.Y.Z' + X.Y'.Z' + X.Y.Z = X‘.(Y'.Z + Y.Z') + X.(Y'.Z' + Y.Z) = X'.(Y  Z) + X.(Y  Z)' = X  (Y  Z) or (X  Y)  Z

14. CS1104-6Gate-level (SSI) Design: Full Adder 14 Gate-level (SSI) Design: Full Adder (4/5)  Circuit for above formulae: C = X.Y + (X  Y).Z S = (X  Y)  Z Full Adder made from two Half-Adders (+ OR gate). (X  Y) XYXY S C Z (XY)

15. CS1104-6Gate-level (SSI) Design: Full Adder 15 Gate-level (SSI) Design: Full Adder (5/5)  Circuit for above formulae: C = X.Y + (X  Y).Z S = (X  Y)  Z Full Adder made from two Half-Adders (+ OR gate). (X  Y) XYXY S C Z (X.Y) Half Adder Half Adder XYXY XYXY Sum Carry Sum Carry Block diagrams.

16. CS1104-6Code Converters16 Code Converters  Code converters – take an input code, translate to its equivalent output code. Code converter Input code Output code  Example: BCD to Excess-3 Code Converter. Input: BCD digit Output: Excess-3 digit

17. CS1104-6BCD-to-Excess-3 Code Converter17 BCD-to-Excess-3 Code Converter (1/2)  Truth table: 1 A C 00 01 11 10 00 01 11 10 D AB CD B XXXX XX A C 00 01 11 10 00 01 11 10 D AB CD B XXXX XX A C 00 01 11 10 00 01 11 10 D AB CD B XXXX XX A C 00 01 11 10 00 01 11 10 D AB CD B XXXX XX 1 111 1 W 1 111 1 1 11 11 11 11 X YZ  K-maps:

18. CS1104-6BCD-to-Excess-3 Code Converter18 BCD-to-Excess-3 Code Converter (2/2) 1 A C 00 01 11 10 00 01 11 10 D AB CD B XXXX XX 11 11 Z A C 00 01 11 10 00 01 11 10 D AB CD B XXXX XX1 111 1 W W = A + B.C + B.D X = B'.C + B‘.D + B.C'.D' Y = C.D + C'.D' Z = D' A C 00 01 11 10 00 01 11 10 D AB CD B XXXX XX 1 111 1 X A C 00 01 11 10 00 01 11 10 D AB CD B XXXX XX1 11 11 Y

19. CS1104-6Block-Level Design Method19 Block-Level Design Method  More complex circuits can also be built using block- level method.  In general, block-level design method (as opposed to gate-level design) relies on algorithms or formulae of the circuit, which are obtained by decomposing the main problem to sub-problems recursively (until small enough to be directly solved by blocks of circuits).  Simple examples using 4-bit parallel adder as building blocks:  (1) BCD-to-Excess-3 Code Conversion  (2) 16-Bit Parallel Adder  (3) Adder cum Subtractor

20. CS1104-64-bit Parallel Adder20 4-bit Parallel Adder (1/4)  Consider a circuit to add two 4-bit numbers together and a carry-in, to produce a 5-bit result: 4-bit Parallel Adder C5C5 C1C1 X2X2 X1X1 Y4Y4 Y3Y3 S4S4 S3S3 S2S2 S1S1 Y2Y2 Y1Y1 X4X4 X3X3 Black-box view of 4-bit parallel adder  5-bit result is sufficient because the largest result is: (1111) 2 +(1111) 2 +(1) 2 = (11111) 2

21. CS1104-64-bit Parallel Adder21 4-bit Parallel Adder (2/4)  SSI design technique should not be used.  Truth table for 9 inputs very big, i.e. 2 9 =512 entries:  Simplification very complicated.

22. CS1104-64-bit Parallel Adder22 4-bit Parallel Adder (3/4)  Alternative design possible.  Addition formulae for each pair of bits (with carry in), C i+1 S i = X i + Y i + C i has the same function as a full adder. C i+1 = X i.Y i + (X i  Y i ).C i S i = X i  Y i  C i

23. CS1104-64-bit Parallel Adder23 4-bit Parallel Adder (4/4)  Cascading 4 full adders via their carries, we get: C1C1 Y 1 X 1 S1S1 FA C2C2 C5C5 Y 2 X 2 S2S2 FA C3C3 Y 3 X 3 S3S3 FA C4C4 Y 4 X 4 S4S4 FA Output Input

24. CS1104-6Parallel Adders24 Parallel Adders  Note that carry propagated by cascading the carry from one full adder to the next.  Called Parallel Adder because inputs are presented simultaneously (in parallel). Also, called Ripple-Carry Adder.

25. CS1104-6BCD-to-Excess-3 Code Converter25 BCD-to-Excess-3 Code Converter (1/2)  Excess-3 code can be converted from BCD code using truth table:  Gate-level design can be used since only 4 inputs. Gate-level design  However, alternative design possible.  Use problem-specific formulae: Excess-3 Code = BCD Code + (0011) 2

26. CS1104-6BCD-to-Excess-3 Code Converter26 BCD-to-Excess-3 Code Converter (2/2) Excess-3 Code = BCD Code + (0011) 2  Block-level circuit: 4-bit Parallel Adder X4X3X2X1X4X3X2X1 Y4Y3Y2Y1Y4Y3Y2Y1 00110011 S4S3S2S1S4S3S2S1 BCD code Excess-3 code unused 0 Cin Cout A BCD-to-Excess-3 Code Converter

27. CS1104-616-bit Parallel Adder27 16-bit Parallel Adder (1/2)  Larger parallel adders can be built from smaller ones.  Example: a 16-bit parallel adder can be constructed from four 4-bit parallel adders: 4-bit // adder X 4..X 1 Y 4..Y 1 C1C1 S 4..S 1 4-bit // adder X 8..X 5 Y 8..Y 5 C5C5 S 8..S 5 4-bit // adder X 12..X 9 Y 12..Y 9 C9C9 S 12..S 9 4-bit // adder X 16..X 13 Y 16..Y 13 C 13 S 16..S 13 C 17 4444 44444444 A 16-bit parallel adder

28. CS1104-616-bit Parallel Adder28 16-bit Parallel Adder (2/2)  Shortened notation for multiple lines. 16-bit parallel adder ripples carry from one 4-bit block to the next. Such ripple-carry circuits are “slow” because of long delays needed to propagate the carries. 4 S 4.. S 1 S 4 S 3 S 2 S 1 is a shortened notation for

29. CS1104-64-bit Parallel Adder cum Subtractor 29 4-bit Parallel Adder cum Subtractor (1/4)  Subtraction can be performed through addition using 2s-complement numbers.  Hence, we can design a circuit which can perform both addition and subtraction, using a parallel adder. 4-bit adder cum subtractor S: control signal for add/subtract X2X2 X1X1 Y4Y4 Y3Y3 Result: either X+Y or X-Y Y2Y2 Y1Y1 X4X4 X3X3

30. CS1104-64-bit Parallel Adder cum Subtractor 30 4-bit Parallel Adder cum Subtractor (2/4)  The control signal S=0 means add S=1 means subtract  Recall that: X-Y = X + (-Y) = X + (2’s complement of Y) = X + (1’s complement of Y) +1 X+Y = X + (Y)

31. CS1104-64-bit Parallel Adder cum Subtractor 31 4-bit Parallel Adder cum Subtractor (3/4)  Design requires: (i) XOR gates: such that: output = Y when S=0 = Y' when S=1 (ii) S connected to carry-in. S = 0 Y Y S = 1 Y' Y

32. CS1104-64-bit Parallel Adder cum Subtractor 32 4-bit Parallel Adder cum Subtractor (4/4)  Adder cum subtractor circuit: Analysis: If S=1, then X + (1's complement of Y) +1 appears as the result. If S=0, then X+Y appears as the result. 4-bit parallel adder X2X2 X1X1 Y4Y4 Y3Y3 Y2Y2 Y1Y1 X4X4 X3X3 S2S2 S1S1 S4S4 S3S3 C S Cin Cout A 4-bit adder cum subtractor

33. CS1104-6Arithmetic Circuits: Adders33 Arithmetic Circuits: Adders  Half adder X Y  Cout  Sum Carry Input bits Output bits x y' S = xy' + x'y x' y xyxy C xyxy S = (x+y)(x'+y') x' y' xyxy C x' y' S = (C+x'y')' xyxy C xyxy C S = x  y Revision

34. CS1104-6Arithmetic Circuits: Adders34 Arithmetic Circuits: Adders  Full adder Sum Carry Input bits Output bits A B  Cout  Cin 0 10 1 00 01 11 10 x yz C = xy + xz + yz 111 1 1 S = x'y'z + x'yz' + xy'z' + xyz 0 10 1 00 01 11 10 x yz 1 1 1 xyxy S = (x  y)  z C = xy + (x  y)z z xyxy xy X' y' z S x' y z' x y' z' xyzxyz C xzxz yzyz xyxy Revision

35. CS1104-6Arithmetic Circuits: Parallel Adders 35 Arithmetic Circuits: Parallel Adders  Example: Adding two 4-bit numbers 2 ways: u Serial (one FA) u Parallel (n FAs for n bits) C1C1 Y 1 X 1 S1S1 C2C2 C5C5 Y 2 X 2 S2S2 C3C3 Y 3 X 3 S3S3 C4C4 Y 4 X 4 S4S4 FA X Y  Cout S CinInput carry Binary no. B Binary no. A Output carry 4-bit sum Revision

36. CS1104-6Arithmetic Circuits: Cascading Adders 36 Arithmetic Circuits: Cascading Adders  4-bit parallel adder:  cascade 4 full adders  classical method: 9 input variables  2 9 = 512 rows in truth table!  Cascading method can be extended to larger numbers, example: 16-bit parallel adder. 4-bit // adder X 4..X 1 Y 4..Y 1 C1C1 S 4..S 1 4-bit // adder X 8..X 5 Y 8..Y 5 C5C5 S 8..S 5 4-bit // adder X 12..X 9 Y 12..Y 9 C9C9 S 12..S 9 4-bit // adder X 16..X 13 Y 16..Y 13 C 13 S 16..S 13 C 17 4444 44444444 Revision

37. CS1104-6Arithmetic Circuits: Cascading Adders 37 Arithmetic Circuits: Cascading Adders  Application: 6-person voting system.  Use FAs and a 4-bit binary parallel adder.  Each FA can sum up to 3 votes. Voter 1 3-bit Output A B  Cout  Cin Voter 2 Voter 3 Voter 4 A B  Cout  Cin Voter 5 Voter 6 Full-adder 1 Full-adder 2  Cout Cin A 12341234 B 12341234 S 12341234 Parallel adder

38. CS1104-6Arithmetic Circuits: Adder- Subtractor 38 Arithmetic Circuits: Adder-Subtractor  Make use of 2’s complement: X - Y = X + (-Y)  2’s complement of Y = Inverting bits in Y and plus 1. When S=0, Cin=0, Z i = Y i  S = X + Y When S=1, Cin=1, Z i = Y i '  S = X + Y' + 1 4-bit parallel adder X2X2 X1X1 Y4Y4 Y3Y3 Y2Y2 Y1Y1 X4X4 X3X3 S2S2 S1S1 S4S4 S3S3 C S Cin Cout Z4Z4 Z3Z3 Z2Z2 Z1Z1 Z i = S.Y i ' + S'.Y i Revision

39. CS1104-6Arithmetic Circuits: Comparator39 Arithmetic Circuits: Comparator (1/3)  Magnitude comparator: compares 2 values A and B, to see if A>B, A=B or A<B.  Classical method requires 2 2n rows in truth table!  We exploit regularity.  How do we compare two 4-bit values A (a 3 a 2 a 1 a 0 ) and B (b 3 b 2 b 1 b 0 )? If (a 3 > b 3 ) then A > B If (a 3 < b 3 ) then A < B If (a 3 = b 3 ) then if (a 2 > b 2 ) ….

40. CS1104-6Arithmetic Circuits: Comparator40 Arithmetic Circuits: Comparator (2/3) Let A = A 3 A 2 A 1 A 0, B = B 3 B 2 B 1 B 0 ; x i = A i.B i + A i '.B i ' A 3 '.B 3 + x 3.A 2 '.B 2 + x 3.x 2.A 1 '.B 1 + x 3. x 2.x 1.A 0 '.B 0 A 3.B 3 ' + x 3.A 2.B 2 ' + x 3.x 2.A 1.B 1 ' + x 3. x 2.x 1.A 0.B 0 ' x 3. x 2.x 1.x 0

41. CS1104-6Arithmetic Circuits: Comparator41 Arithmetic Circuits: Comparator (3/3) A3A2A1A0A3A2A1A0 4-bit comp (A < B) (A > B) (A = B) B3B2B1B0B3B2B1B0 01100110 10101010 100100 Block diagram of a 4-bit magnitude comparator

42. CS1104-6Calculation of Circuit Delays42 Calculation of Circuit Delays (1/5)  In general, given a logic gate with delay, t. If inputs are stable at times t 1,t 2,..,t n, respectively; then the earliest time in which the output will be stable is: max(t 1, t 2,.., t n ) + t Logic Gate t1t1 t2t2 tntn :: max (t 1, t 2,..., t n ) + t  To calculate the delays of all outputs of a combinational circuit, repeat above rule for all gates.

43. CS1104-6Calculation of Circuit Delays43 Calculation of Circuit Delays (2/5)  As a simple example, consider the full adder circuit where all inputs are available at time 0. (Assume each gate has delay t.) where outputs S and C, experience delays of 2t and 3t, respectively. XYXY S C Z max(0,0)+t = t t 0 0 0 max(t,0)+t = 2t max(t,2t)+t = 3t 2t

44. CS1104-6Calculation of Circuit Delays44 Calculation of Circuit Delays (3/5)  More complex example: 4-bits parallel adder. C1C1 Y 1 X 1 S1S1 FA C2C2 C5C5 Y 2 X 2 S2S2 FA C3C3 Y 3 X 3 S3S3 FA C4C4 Y 4 X 4 S4S4 FA 0 00000000

45. CS1104-6Calculation of Circuit Delays45 Calculation of Circuit Delays (4/5)  Analyse the delay for the repeated block: where X i, Y i are stable at 0t, while C i is assumed to be stable at mt. Full Adder XiYiCiXiYiCi S i C i+1 0 0 mt  Performing the delay calculation gives: XiYiXiYi SiSi C i+1 CiCi max(0,0)+t = t t 0 0 mt max(t,mt)+t max(t,mt)+2t max(t,mt)+t

46. CS1104-6Calculation of Circuit Delays46 Calculation of Circuit Delays (5/5)  Calculating: When i=1, m=0: S 1 = 2t and C 2 = 3t. When i=2, m=3: S 2 = 4t and C 3 = 5t. When i=3, m=5: S 3 = 6t and C 4 = 7t. When i=4, m=7: S 4 = 8t and C 5 = 9t.  In general, an n-bit ripple-carry parallel adder will experience: S n = ((n-1)*2+2)t C n+1 = ((n-1)*2+3)t as their delay times.  Propagation delay of ripple-carry parallel adders is proportional to the number of bits it handles.  Maximum Delay: ((n-1)*2+3)t

47. CS1104-6Faster Circuits47 Faster Circuits  Three ways of improving the speed of these circuits:  (i) Use better technology (e.g. ECL faster than TTL gates), BUT (a) faster technology is more expensive, needs more power, lower-level of integrations. (b) physical limits (e.g. speed of light, size of atom).  (ii) Use gate-level designs to two-level circuits! (use sum- of-products/product-of-sums) BUT  (a) complicated designs for large circuits.  (b) product/sum terms need MANY inputs!  (iii) Use clever look-ahead techniques BUT there are additional costs (hopefully reasonable).

48. CS1104-6Look-Ahead Carry Adders48 Look-Ahead Carry Adder (1/6)  Consider the full adder: where intermediate signals are labelled as P i, G i, and defined as: P i = X i  Y i G i = X i.Y i  The outputs, C i+1,S i, in terms of P i,G i,C i, are: S i = P i  C i …(1) C i+1 = G i + P i.C i …(2)  If you look at equation (2), G i = X i.Y i is a carry generate signal P i = X i  Y i is a carry propagate signal XiYiXiYi SiSi C i+1 CiCi PiPi GiGi

49. CS1104-6Look-Ahead Carry Adder49 Look-Ahead Carry Adder (2/6)  For 4-bit ripple-carry adder, the equations to obtain four carry signals are: C i+1 = G i + P i.C i C i+2 = G i+1 + P i+1.C i+1 C i+3 = G i+2 + P i+2.C i+2 C i+4 = G i+3 + P i+3.C i+3  These formula are deeply nested, as shown here for C i+2 : CiPiCiPi C i+1 GiGi P i+1 G i+1 C i+2 4-level circuit for C i+2 = G i+1 + P i+1.C i+1

50. CS1104-6Look-Ahead Carry Adder50 Look-Ahead Carry Adder (3/6)  Nested formula/gates cause ripple-carry propagation delay.  Can reduce delay by expanding and flattening the formula for carries. For example, C i+2 C i+2 = G i+1 + P i+1.C i+1 = G i+1 + P i+1.(G i + P i.C i ) = G i+1 + P i+1.G i + P i+1.P i.C i  New faster circuit for C i+2 C i P i P i+1 GiGi G i+1 C i+2

51. CS1104-6Look-Ahead Carry Adder51 Look-Ahead Carry Adder (4/6)  Other carry signals can also be similarly flattened. C i+3 = G i+2 + P i+2 C i+2 = G i+2 + P i+2 (G i+1 + P i+1 G i + P i+1 P i C i ) = G i+2 + P i+2 G i+1 + P i+2 P i+1 G i + P i+2 P i+1 P i C i C i+4 = G i+3 + P i+3 C i+3 = G i+3 + P i+3 (G i+2 + P i+2 G i+1 + P i+2 P i+1 G i + P i+2 P i+1 P i C i ) = G i+3 + P i+3 G i+2 + P i+3 P i+2 G i+1 + P i+3 P i+2 P i+1 G i + P i+3 P i+2 P i+1 P i C i  Notice that formulae gets longer with higher carries.  Also, all carries are two-level “sum-of-products” expressions, in terms of the generate signals, Gs, the propagate signals, Ps, and the first carry-in, C i.

52. CS1104-6Look-Ahead Carry Adder52 Look-Ahead Carry Adder (5/6)  We employ the look-ahead formula in this lookahead-carry adder circuit:

53. CS1104-6Look-Ahead Carry Adder53 Look-Ahead Carry Adder (6/6)  The 74182 IC chip allows faster lookahead adder to be built.  Maximum propagation delay is 4t (t to get generate & propagate signals, 2t to get the carries and t for the sum signals) where t is the average gate delay.

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