1. Arithmetic Operations and Circuits
Chapter 7
Arithmetic Operations and Circuits
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2. Binary Arithmetic Addition Subtraction Multiplication Division
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3. Binary Arithmetic Addition
when the sum exceeds 1, carry a 1 over to the next-more-significant column
0 + 0 = 0 carry 0
0 + 1 = 1 carry 0
1 + 0 = 1 carry 0
1 + 1 = 0 carry 1
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4. Binary Arithmetic Addition General form
A0 + B0 = 0 + Cout
summation symbol
carry-out
See Table 7-1
carry-out is added to the next-more-significant column as a carry-in
See Figure 7-1
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5. William Kleitz Digital Electronics with VHDL, Quartus® II Version
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6. Figure 7-1
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7. Binary Arithmetic Subtraction 0 - 0 = 0 borrow 0 0 - 1 = 1 borrow 1
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8. Binary Arithmetic Subtraction General form
A0 - B0 = R0 + Bout
remainder is R0
borrow is Bout
See Table 7-2
When A0 borrows from its left, A0 increases by 2
See Figure 7-2
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9. William Kleitz Digital Electronics with VHDL, Quartus® II Version
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10. Figure 7-2
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11. Binary Arithmetic Multiplication
multiply the 20 bit of the multiplier times the multiplicand
multiply the 21 bit of the multiplier times the multiplicand. Shift the result one position to the left before writing it down
repeat step 2 for the 22 bit of the multiplier, etc.
take the sum of the partial products to get the final product
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12. Binary Arithmetic Division the same as decimal division
see Example 7-4
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13. William Kleitz Digital Electronics with VHDL, Quartus® II Version
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14. Two’s-Complement Representation
Both positive and negative numbers can be represented
Binary subtraction is simplified
Groups of eight
Most significant bit (MSB) signifies positive or negative
sign bit
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15. Two’s-Complement Representation
Sign bit
0 for positive
1 for negative
Range of positive numbers (8-bit)
to (0 to 128)
Range of negative numbers (8-bit)
to (-1 to -128)
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16. Two’s-Complement Representation
See Table 7-3
Decimal-to-Two’s-Complement Conversion
If number is positive, convert directly
If number is negative
complement each bit (one’s complement)
add 1
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17. William Kleitz Digital Electronics with VHDL, Quartus® II Version
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18. Two’s-Complement Representation
Two’s-Complement-to-Decimal Conversion
If number is positive, convert directly
If number is negative
complement entire two’s-complement number
add 1
convert this to decimal
result will be a negative number
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19. Two’s-Complement Arithmetic
Addition
regular binary addition
Subtraction
convert number to be subtracted to a negative two’s-complement number
carry out of the MSB is ignored
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20. Hexadecimal Arithmetic
4 binary bits as a single hexadecimal digit
Addition
add the digits in decimal
if sum is less than 16, convert to hexadecimal
is sum is more than 16, subtract 16, convert to hexadecimal and carry 1 to the next-more-significant column
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21. Hexadecimal Arithmetic
Subtraction
when you borrow, the borrower increases by 16
See Example 7-15
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22. William Kleitz Digital Electronics with VHDL, Quartus® II Version
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23. BCD Arithmetic
Group 4 binary digits to get combinations for 10 decimal digits
Range of valid numbers 0000 to 1001
Addition
add as regular binary numbers
if sum is 9 or less - OK
if sum is greater than 9 or if carry out generated
add 6 (0110) saving any carry out
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24. Arithmetic Circuits Medium-scale-integration (MSI) circuits
Basic Adder Circuit
See Figure 7-5
Half-Adder
0 HIGH when A or B HIGH, but not both
exclusive-OR function
Cout high when A and B HIGH
AND function
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25. Figure 7-5
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26. Arithmetic Circuits Half-Adder Full-Adder See Figures 7-6 and 7-7
1 HIGH when 3 inputs are odd
even parity generator
see Figure 7-8
Cout HIGH when any two inputs are HIGH
3 ANDs and an OR
see Figure 7-9
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27. Figure 7-6
Figure 7-7
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28. Figure 7-8
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29. Figure 7-9
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30. Arithmetic Circuits Complete Full-Adder Block diagrams See Figure 7-10
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31. Figure 7-10
Figure 7-14
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32. Four-Bit Full-Adder ICs
Four full-adders in a single package
Will add two 4-bit binary words plus one incoming carry
See Table 7-5 and Figure 7-16
Fast-look-ahead carry
evaluates 4 low-order inputs
high-order bits added at same time
eliminates waiting for propagation ripple
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33. William Kleitz Digital Electronics with VHDL, Quartus® II Version
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34. Figure 7-16
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35. VHDL Adders Using Integer Arithmetic
Addition process using the addition operator and integer data type
integer data type allows inputs with numeric values other than 1 or 0
arithmetic operations can be performed
specify range of variable
A VHDL 4 bit binary adder and simulation
see figure 7-18
see figure 7-19
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36. Figure 7-18
Figure 7-19
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37. System Design Applications
Two’s-Complement Adder/Subtractor Circuit
See Figure 7-21
BCD Adder Circuit
See Figure 7-22
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38. Figure 7-22
Figure 7-21
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39. Arithmetic/Logic Units
ALU is a multipurpose device
Mode Control (M)
arithmetic
logic
see Figure 7-23
Function Select
selects specific function to be performed
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40. Figure 7-23
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41. Figure 7-23 (continued)
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42. CPLD Applications with VHDL and LPMs
CPLD based arithmetic circuits using macrofunctions, VHDL, and LPMs
library of parameterized modules are provided in Quartus II software to speed the design process
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43. CPLD Applications with VHDL and LPMs
Example 7-25
a 4 bit adder using the macrofunction
see figures 7-25 and 7-26
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44. Figure 7-25
Figure 7-26
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45. CPLD Applications with VHDL and LPMs
Example 7-26
an 8 bit adder/subtractor using the + and – arithmetic operators
see figures 7-27 and 7-28
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46. Figure 7-27
Figure 7-28
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47. CPLD Applications with VHDL and LPMs
Example 7-27
a BCD adder based on figure 7-22
see figures 7-29 and 7-30
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48. Figure 7-29
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49. Figure 7-30
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50. CPLD Applications with VHDL and LPMs
Example 7-28
an adder/subtractor using LPMs
see figures 7-31, 7-32, 7-33
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51. Figure 7-31
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52. Figure 7-32
Figure 7-33
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53. Summary
The binary arithmetic functions of addition, subtraction, multiplication and division can be performed bit by bit using several of the same rules of regular base 10 arithmetic.
The two’s-complement representation of binary numbers is commonly used by computer systems for representing positive and negative numbers.
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54. Summary
Two’s-complement arithmetic simplifies the process of subtraction of binary numbers.
Hexadecimal addition and subtraction is often required for determining computer memory space and locations.
When performing BCD addition a correction must be made for sums greater than 9 or when a carry to the next more significant digit occurs.
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55. Summary
Binary adders can be built using simple combinational logic circuits.
A half-adder is required for addition of the least significant bits
A full-adder is required for addition of the more significant bits.
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56. Summary
Multibit full-adder ICs are commonly used for binary addition and two’s-complement arithmetic.
Arithmetic/logic units are multipurpose ICs capable of providing several different arithmetic and logic functions.
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57. Summary
The logic circuits for adders can be described in VHDL using integer arithmetic.
The Quartus II software provides 7400-series macrofunctions and a Library of Parameterized Modules to ease in the design of complex digital systems.
Conditional assignments can be made using the IF-THEN-ELSE VHDL statements.
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