1. EKT 124 / 3 DIGITAL ELEKTRONIC 1
CHAPTER 3
Sequential Logic/ Circuits:
Shift Register

2. Shift Register Basic shift register function
Serial in/Serial out shift registers (SISO)
Serial in/Parallel out shift registers (SIPO)
Parallel in/Serial out shift registers (PISO)
Parallel in/Parallel out shift registers
(PIPO)
Bidirectional shift registers
Shift register applications

3. Sequential Logic Circuits
Combinational outputs
Memory outputs
Combinational logic
Memory elements
Inputs
Sequential circuit = Combinational logic + Memory Elements
Current State of A sequential Circuit:
Value stored in memory elements (value of state variables).
State transition:
A change in the stored values in memory elements thus changing the sequential circuit from one state to another state.

4. Registers A register is a memory device that can be used to
store more than one-bit information
A register is usually realized as several flip-flops
with common control signals that control the
movement of data to and from the registers
……….

5. Registers An n-bit register is a collection of n D flip-flops with a
common clock used to store n related bits.
74LS175
Example:
74LS175 4-bit register 1D 1Q D Q
CLR Q
/1Q
CLK
CLR 4Q 3Q 2Q 1Q
74LS175 1D 2D 3D 4D 2Q 2D D Q
CLR Q
/2Q 3Q 3D D Q
CLR Q
/3Q 4Q 4D D Q
CLR Q
/4Q
CLK
/CLR

6. Shift Registers
Multi-bit register that moves stored data bits left/right ( 1 bit
position per clock cycle)
Shift Left is towards MSB
LSI
Q3 Q2 Q1 Q0
LSI
Q3 Q2 Q1 Q0
Shift Right (or Shift Up) is towards MSB
RSI
Q3 Q2 Q1 Q0
RSI
Q3 Q2 Q1 Q0

7. Basic Shift Register Functions
consist of an arrangement of flip-flops
important in applications involving storage and
transfer of data (data movement) in digital system
used for storing and shifting data (1s and 0s)
entered into it from an external source and
possesses no characteristic internal sequence of
states.
Generally, D flip-flops are usually used to store and move data

8. The flip-flop as a storage element
When a 1 is on D, Q becomes a 1 at triggering edge of CLK or remains a 1 if already in the SET state
When a 0 is on D, Q becomes a 0 at triggering edge of CLK or remains a 0 if already in the RESET state

9. Basic data movement in shift registers (Four bits are used for illustration. The bits move in the direction of the arrows.)

10. Types of Shift Registers
Serial In / Serial Out Shift Registers (SISO)
Serial In /Parallel Out Shift Registers (SIPO)
Parallel In / Serial Out Shift Registers (PISO)
Parallel In / Parallel Out Shift Registers (PIPO)

11. Serial In, Serial Out Shift Registers (SISO)
D Q
CLK
Serial In
Clock
Serial Out
SRG n
> SI SO
For a n-bit SRG:
Serial Out = Serial In delayed by n clock period
4-bit shift register example:
Serial in:
Serial out:
Clock:

12. Serial In, Serial Out Shift Registers (SISO)

15. Serial In, Serial Out Shift Registers (SISO)

16. Serial In, Parallel Out Shift registers (SIPO)
SRG n
> SI 1Q 2Q nQ
D Q
CLK
Serial In
Clock nQ 2Q 1Q SO
Serial to Parallel Converter
Example: 4-bit shift register
serin:
1Q:
2Q:
3Q:
4Q:
clock:

17. Serial In, Parallel Out Shift registers (SIPO)
Data bits entered serially (right-most bit first)
Difference from SISO is the way data bits are taken out of the register – in parallel.
Output of each stage is available

18. Example: The states of 4-bit register (SRG 4) for the data input and clocks waveforms.
Assume the register initially contains all 1s

19. Parallel In, Serial Out Shift Registers (PISO)
CLOCK
LOAD/SHIFT
Serial in 1Q S
D Q
CLK 1D L 2Q S
D Q
CLK 2D L
Parallel to Serial Converter
Load/Shift=1
Di Qi
Load/Shift=0
Qi Qi+1 NQ S
D Q
CLK
Serial out ND L

20. 4-bit parallel in/serial out shift register (PISO)

21. Parallel In, Parallel Out Shift Register (PIPO)
CLOCK
LOAD/SHIFT
Serial In S
D Q
CLK 1Q 1D L S
D Q
CLK 2Q 2D L
General Purpose:
Makes any kind of (left) shift register S
D Q
CLK NQ ND L

22. Parallel In, Parallel Out Shift Register (PIPO)
Immediately following simultaneous entry of all data bits, it appears on parallel output.

23. Types of Shift Registers
Generally, shift registers operate in one of four different modes with the basic movement of data through a shift register being:
1) SIPO - the register is loaded with serial data, one bit at a time, with the stored data being available in parallel form.
2) SISO - the data is shifted serially "IN" and "OUT" of the register, one bit at a time in either a left or right direction under clock control. 3) PISO - the parallel data is loaded into the register simultaneously and is shifted out of the register serially one bit at a time under clock control.
4) PIPO - the parallel data is loaded simultaneously into the register, and transferred together to their respective outputs by the same clock pulse.

24. Bi-directional Shift Registers
Data can be shifted left
Data can be shifted right
A parallel load maybe possible
74HC194 is an bidirectional universal shift register

25. Bi-directional Universal Shift Registers
4-bit Bi-directional Universal (4-bit) PIPO
CLK
CLR S1 S0
LIN
D QD
C QC
B QB
A QA
RIN 11 1 10 9 7 6 4 5 3 2 12 13 14 15
74x194
Modes:
Hold
Load
Shift Right
Shift Left
R L
Mode Next state
Function S1 S QA* QB* QC* QD*
Hold QA QB QC QD
Shift right/up RIN QA QB QC
Shift left/down QB QC QD LIN
Load A B C D

26. 4-bit Johnson counters Serial output connected back to serial input
The complement of the output (Q’) is fedback into 1st FF.

27. 4-bit Johnson Ring Counter
Truth Table for a 4-bit Johnson Ring Counter
4-bit Johnson Ring Counter
Clock Pulse No
FFA
FFB
FFC
FFD 1 2 3 4 5 6 7
This inversion of Q before it is fed back to input D causes the counter to "count" in a different way. Instead of counting through a fixed set of patterns like the normal ring counter such as for a 4-bit counter, "0001"(1), "0010"(2), "0100"(4), "1000"(8) and repeat, the Johnson counter counts up and then down as the initial logic "1" passes through it to the right replacing the preceding logic "0".
A 4-bit Johnson ring counter passes blocks of four logic "0" and then four logic "1" thereby producing an 8-bit pattern.
As the inverted output Q is connected to the input D this 8-bit pattern continually repeats. For example, "1000", "1100", "1110", "1111", "0111", "0011", "0001", "0000”

28. Five-bit Johnson counters

29. 10-bit ring counter
Assume initial
state:
(Q0---Q9) =

30. 4-bit Ring Counter
Synchronous Ring Counter is preset so that exactly one data bit in the register is set to logic "1" with all the other bits reset to "0".
To achieve this, a "CLEAR" signal is firstly applied to all the flip-flops together in order to "RESET" their outputs to a logic "0" level and then a "PRESET" pulse is applied to the input of the first flip-flop (FFA) before the clock pulses are applied.
This then places a single logic "1" value into the circuit of the ring counter .
On each successive clock pulse, the counter circulates the same data bit between the four flip-flops over and over again around the "ring" every fourth clock cycle.
In order to cycle the data correctly around the counter we must first "load" the counter with a suitable data pattern as all logic "0"'s or all logic "1"'s outputted at each clock cycle would make the ring counter invalid.

31. otational Movement of a Ring Counter
ROTATION OF RING COUNTER
Since the ring counter has four distinct states, it is also known as a "modulo-4" or "mod-4" counter with each flip-flop output having a frequency value equal to one-fourth or a quarter (1/4) that of the main clock frequency.

32. Shift Register Applications
State Registers
Shift registers are often used as the state register in a sequential device. Usually, the next state is determined by shifting right and inserting a primary input or output into the next position (i.e. a finite memory machine)
Very effective for sequence detectors
Serial Interconnection of Systems
keep interconnection cost low with serial interconnect
Bit Serial Operations
Bit serial operations can be performed quickly through device iteration
Iteration (a purely combinational approach) is expensive (in terms of # transistors, chip area, power, etc).
A sequential approach allows the reuse of combinational functional units throughout the multi-cycle operation

33. Shift Register Applications Example: Serial Interconnection of Systems
CLOCK
Control
Circuits
Control
Circuits
Receiver
Transmitter
/SYNC
Parallel Data from
A-to-D converter
Parallel Data to D-to-A converter
Serial-to-parallel converter
Parallel-to-serial converter
Serial DATA n
One bit n

34. Shift Register Applications Example: 8-Bit Serial Adder
... 7 6 5
> x7 x6 x5 x0 y7 y6 y5 y0 FA
Cout S
Cin A B
D Q
CLK
CLR
CLEAR_C z7 z6 z5 z0
CTL
Sequential Implementation of:
Z[7..0] = X[7..0] + Y[7..0] V

35. Shift Register Applications Example: The shift register as a time-delay device

36. Shift Register Applications Example: Simplified logic diagram of a serial-to-parallel converter