1. Lecture 21: LM3S9B96 Microcontroller – System Control

2. Stellaris® LM3S9B96 Microcontroller Data Sheet Chapter 6 System Control

3. zSystem control configures the overall operation of the device and provides information about the device. zreset control zNMI operation zpower control zclock control zlow-power modes

4. Power Control zWithin the MCU, an integrated LDO regulator is used to provide power to the majority of the MCU's internal logic zVoltage output can be programmed z1.08v ~ 1.35v, max 60ma

5. Clock Control zFundamental Clock Sources zPrecision Internal Oscillator (PIOSC): on-chip clock source, 16MHz + 1%  Main Oscillator (MOSC): an external crystal is connected across the OSC0 input and OSC1 output pins; if PLL is being used, crystal frequency range 3.579545 MHz through 16.384 MHz (inclusive); if not, between 1 MHz and 16.384 MHz zInternal 30-kHz Oscillator: on-chip clock source, 30kHz + 50%, used during Deep-Sleep power-saving modes zThe internal system clock can be derived from all above clock sources and the output of PLL and PIOSC divided by four (4MHz + 1%)

6. Clock Configuration The Run-Mode Clock Configuration (RCC) and Run- Mode Clock Configuration 2 (RCC2) registers provide control for the system clock zSource of clocks in sleep and deep-sleep modes zSystem clock derived from PLL or other clock source zEnabling/disabling of oscillators and PLL zClock divisors zCrystal input selection

7. Main Clock Tree

8. Initialization and Configuration zThe PLL is configured using direct register writes to the RCC/RCC2 register zThe steps required to successfully change the PLL-based system clock are:  1. Bypass the PLL and system clock divider by setting the BYPASS bit and clearing the USESYS bit in the RCC register  2. Select the crystal value ( XTAL ) and oscillator source ( OSCSRC ), and clear the PWRDN bit in RCC/RCC2.  3. Select the desired system divider ( SYSDIV ) in RCC/RCC2 and set the USESYS bit in RCC  4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register  5. Enable use of the PLL by clearing the BYPASS bit in RCC/RCC2

9. Register Map zThe System Control base address: 0x400F.E000 zTable 6-8 on page 117 lists the System Control registers, grouped by function. zKey registers: zRCC/RCC2, GPIOHBCTL, RCGCn zCheck those registers with their descriptions