1. Preliminary Design Review NASA Wireless Smart Plug (NWSP) Experimental Control Logic Labs October 29 th, 2012

2. PDR Agenda 1. Update of documents developed and baselined since SDR 2. Matured Concept of Operations 3. Updates to Engineering Specialty Plans 4.Top-level Requirements and Flowdown to the next level of requirements since SDR 5. Review Design-to Specifications (hardware and software) and Drawings, Verification and Validation plans, and Interface documents at lower levels; CAD model for all physical components of the system 6.Trade Studies that have been preformed since SDR and their results 7.Engineering Development Tests and Results 8.Select a baseline design solution 9.Review and discuss internal and external interface design solutions (and any interface control documents needed). This includes interface information provided by NASA since SDR 10.Review system operations 11.Design Analyses and Results 12.Risk Management Plan 13.Cost and Schedule data 2

3. Update of Documents Developed and Baselined  System Architecture  Lower level details provided to depict the use of NASA requested components based on the X-Hab Solicitation  Functional Block Diagram  Fuses in primary 28V-DC and 120V-DC load lines have been removed after NASA requirement’s were clarified that the NWSP is not to operate as a safety device  Nivis ISA100.11a Release Version  Habitat Demonstration Unit (HDU) gateway currently running release 2.6.39  HDU VN210 firmware currently running version 4.3.14 (Upg_VN210_FullAPI_SpeedupSPI_ExtWakeup_v04_03_14) 3

4. Matured System Architecture 4 Nivis VersaRouter 900 Master Control Unit Windows OS LabVIEW GUI 1 sample/second ISA100.11a IEEE 802.15.4 NASA Wireless Smart Plug DSHNetworkDSHNetwork End Device 120V-DC or 28V-DC 120V-DC and/or 28V-DC Nivis VersaNode 210

5. Matured Concept of Operations 5 NASA Wireless Smart Plug (NWSP) is a proof-of-concept prototype Installed in the Deep Space Habitat (DSH) mock-up for testing and evaluation purposes only (not space qualified) Used to monitor and control power usage of DSH and its installed equipment Monitor current draw from end device, and define actions based on measurement (i.e. wireless communication, manual disconnect, load shedding).

6. Updates to Engineering Specialty Plans  Nivis Equipment that was supplied by NASA on October 26 th :  PCB with MSP430 and Nivis 210 Radio  Nivis VersaRouter 900  Nivis equipment to be supplied by NASA:  Embedded software for MSP430 and Nivis 210 Radio 6

7. Top-Level Requirements 7  Power Control  Support for 120V/28V DC  Near real-time monitoring  Fail safe  Windows based master control unit  Communications  Wireless configuration, control, monitoring and reporting  Data rate: 1 sample/second  Use a Nivis VN210 radio  Support a Nivis VR900 router Standards: SPI, ISA 100.11a  Form Factor & Fit  Small form factor  Cannon-type connector  Integration with DSH  Deliver five NWSP units for evaluation

8. Requirements Flow Down 1/3 Power Control VoltagesMonitorFail SafeThresholdGUI 28VDC 120VDC 0 to 5A 3% Full Scale 0 to 5A 0.1A Inc. Alert Standalone Executable Windows OS 8

9. Requirements Flow Down 2/3 Communications Data RateEquipmentProtocol 1 sample/s Alert Within 3s Nivis VN210 Nivis VR900 ISA100.11a IEEE 802.15.4 SPI 9

10. Requirements Flow Down 3/3 Form Factor & Fit SizeIntegration 3” x 3” x 3” Cannon-type Connector 5 NWSP DSH Install 10

11. Design-to Specifications 11  Voltage:  Input: 28VDC and/or 120VDC  Output: 28VDC or 120VDC  Monitor Current: 5A, ± 3% of full scale  Data Collection: 1 sample/second  User Interface: Standalone application on Windows-based MCU.  Communication:  Integrate into DSH wireless mesh with Nivis VR 900 gateway  Radio: Nivis VN 210  Standard: ISA100.11a  Size: 3” x 3” x 3” target.  Power Consumption: Minimal  Deliverables: 5 NWSP units, installed on DSH mockup.

12. CAD Model for Physical Components 12

13. Trade Studies and Results: Current Sensor 13 DeviceTypeProsConsCost ACS714Hall Effect  Small package  Negligible power dissipation  Single 5V supply  40A Range Requires offset, gain, and low pass filter $3.89 CMS2015 MagnetoResistive Current Sensor  Electrical Isolation  15A Range  Small package  Bipolar 15V supply  Relatively expensive $35.20 VCS1625High Precision Shunt Resistor  Very small package  Non inductive, non capacitive  No ringing  Power Dissipation  Heat $20

14. Trade Studies and Results: 120VDC to 28VDC Conversion 14 DeviceTypeProsConsCost 667-ERA- 8AHD300V Voltage Divider Inexpensive Small package Power dissipation Heat Fluctuations in output $2.53 MC33363B High Voltage Switching Regulator Small Package Inexpensive Negligible heat Noisy Large current draw of >1A Requires 40V supply $1.60 TL783High Voltage Linear Regulator Adjustable VoutLimited output current Significant waste heat $2.55

15. Trade Studies and Results: Voltage Regulator 15 DeviceTypeProsConsCost LM317L Linear Voltage Regulator Low output noise Programmable output Cheap  Inefficient  Heat $.49 ADP111Switching Regulator  Efficient  Low Heat  Relatively Expensive$2.44 N/A?Hybrid Regulator  Efficient  Low Heat  Low Noise  Larger space required  Relatively Expensive N/A?

16. Trade Studies and Results: Voltage Switch 16 DeviceTypeProsConsCost Micropac 53238 Optocoupled Power Mosfet Small package Operates up to 125V Can handle 5A continuous Radiation tolerant Can be controlled with pin from MSP430 Heat Power dissipation Long lead time Unknown AV3712613Relay Can be controlled with pin from MSP430 Inexpensive Mechanical Power dissipation $1.61 SH20DC20-16High Power DC Solid-State Relay Can handle up to 20A continuous Low control voltage of 3.5V Can be controlled with pin from MSP430 Large$23.56

17. Trade Studies and Results: Connector 17 DeviceManufacturerProsConsCost HBL2513Hubbell Operates up to 208V Can handle 20A continuous Fits NASA requirement Available locally Locking Not quarter turn$73.44 Veam GRHCannon Operates up to 250V Can handle 15A continuous Quarter turn locking High shock and vibration resistance Fits NASA requirement Not available locallyUnknown PDS-222-4AmphenolOperates up to 200V Can handle 10A continuous Designed for space operation Quarter turn locking No 5 pin layout available Not available locally Unknown

18. Trade Studies and Results: Microcontroller 18 ManufacturerMicrocontrollerProsCons Price per Unit Texas Instruments MSP430F5438A Large memory size of 256KB Low operating voltage (1.8 ~ 3.6V) High cost$11.73 MicrochipPIC24FJ128GA110 Cost Less precise A/D convertor of 10 bits $4.76 FreescaleMC56F8257VLH Fast processing speed of 60MHz No UART communication Higher supply voltage necessary $7.15

19. Engineering Development Tests: Analog-to-Digital Converter  12-bit ADC Internal to MSP430F5438A  Internal Reference (2.5V)  Sample-and-Hold  14 External Channels 19 Offset Gain LPF

20. Baseline Design Solution: Functional Block Diagram Overview 20

21. Functional Block Diagram: Voltage Step Down and Regulation 21

22. Functional Block Diagram: Current Sense and Disconnect 22

23. Functional Block Diagram: Nivis VN210 SPI Interfacing 23

24. Internal and External Interface Design Solutions: SPI Serial Peripheral Interface Bus (SPI)  Synchronous serial data link standard  Full duplex mode  Master/Slave mode where the master device initiates the data frame  Multiple slave devices are allowed with individual slave select (chip select) lines  The SPI bus specifies four logic signals:  SCLK: serial clock (output from master)  MOSI: master output, slave input (output from master)  MISO: master input, slave output (output from slave)  SS: slave select (active low, output from master) 24

25. Internal and External Interface Design Solutions: SPI 25 Advantages Full duplex communication Complete protocol flexibility for the bits transferred Typically lower power requirements due to less circuitry (including pull up resistors) Slaves use the master's clock, and don't need precision oscillators Slaves don't need a unique address — unlike I²C or GPIB or SCSI Transceivers are not needed Uses only four pins on IC packages, and wires in board layouts or connectors; fewer than parallel interfaces At most one unique bus signal per device (chip select); all others are shared Not limited to any maximum clock speed, enabling potentially high throughput Disadvantages No in-band addressing; out-of-band chip select signals are required on shared buses No hardware flow control by the No hardware slave acknowledgment Supports only one master device No error-checking protocol is defined Generally prone to noise spikes causing faulty communication Only handles short distances compared to RS-232, RS-485, or CAN-bus SPI does not support hot plugging (dynamically adding nodes).

26. System Operations: Initialization 26 Connect NWSP male input receptacle to DSH Run LabVIEW GUI executable Request parameters from NWSP configuration Set end device parameters Current Threshold Priority Test connection between NWSP and GUI Established Connection? Reset physical connection and executable No Parameters Set? Yes No Connect end device to NWSP female output receptacle Yes (A) Mode

27. System Operations: Standard Operation 27 (A) Close switch of primary supply line to allow end device operation NWSP measures actual current and voltage(s) Actual Exceed Threshold? Compare actual current against configured threshold current Send all measured values to GUI Actual Current of Primary Voltage Point 1 through 7 Mode? Send all measured values to GUI Yes No Send all measured values to GUI Prompt user to disconnect Manual Automatic Disconnect Primary supply line from end device Disconnect Primary supply line from end device Notify user of disconnect User Request Disconnect? No Yes (B) (E or F) (D) (C)

28. System Operations: Disconnect and Reset 28 (B) Disconnect Primary supply line from end device Disconnect Primary supply line from end device Notify user of disconnect Prompt user to reconnect User Reconnect? Wait for user to manually reconnect No Reconnect Device Yes (F) (D) User Disconnect? (C) YesNo (E)

29. GUI Updates - Detailed View

30. GUI Updates

31. Master Control Software Logic

33. Design Analyses: Sampling and Decision Algorithm  Process of averaging multiple samples for noise compensation through statistical analysis:  Defining the population of concern  Specifying a sampling frame, a set of items or events possible to measure  Specifying a sampling method for selecting items or events from the frame  Determining the sample size  Implementing the sampling plan  Sampling and data collecting  Factors  Nature and quality of the frame  Availability of auxiliary information about units on the frame  Accuracy requirements, and the need to measure accuracy  Whether detailed analysis of the sample is expected  Cost/operational concerns 33

34. Design Analyses: Power Budget 34

35. 35 Risk Management Plan: PMI Risk Management Process Identify Evaluate Develop Response Control

36. Risk Prioritization Matrix 36 PriorityTotalOverallRiskComparison 37High1. Project goes overschedule 91Low2. Injury or damage from 120V source 1212 100Low3. Funding delayed 1 2 3 3 110High4. Delay in parts procurement. 1 2 3 4 4 4 28High 5. Solving 120V/28V available power problem 1 2 3 4 5 5 55Medium6. Limited financial resources 1 2 3 4 5 6 6 6 6 6 73Low7. Loss of a team member 1 2 3 4 5 6 7 7 7 82Low8. Unable to source proper 120V DC 1 2 3 4 5 6 7 8 8 8 8 8 8 8 46Medium9. Further revisions necessary 1 2 3 4 5 6 7 8 9 9 9 9 64Medium10. Selected solution found unfeasible 1 2 3 4 5 6 7 8 9 10 10 10 10 10 10 10 10 10

37. Risk Evaluation 37 PROBABILITY OF OCCURRENCE SEVERITY OF IMPACT LOW HIGH LOW 54 6,91 10 3782 1.Project over-schedule 2.Injury/damage from 120V 3.Funding delayed 4.Delay in parts 5.Solving 120V step-down 6.Limited financial resources 7.Loss of a team member 8.Unable to source 120V DC 9.Further revisions necessary 10.Selected solution found unfeasible Legend

38. Cost Data 38 NASA Cost Sharing Labor$40,915 Travel$3,000 Equipment$5,000 (TI) ODCs$5,000 Overhead/Indirect$22,501 (TAMU) _____________________________________________ Total Cost to Sponsor$48,915 $27,501 Actual Project Value 76,416

39. Capstone Labor  Total # of Boxes: 133  Total # of Work Packages: 95  Expected Number of Man Hours: 2259 Hours  Research: 160 Hours  Design: 363 Hours  Simulation: 60 Hours  Implementation: 370 Hours  Testing: 260 Hours  Documentation: 1046 Hours  Close Out: 6 Hours 39

40. Gantt Chart

41. NASA Deliverables 41 DateActivityDeliverable 1/8/12Kickoff MeetingDraft System Design Process (SDP) 19/9/12SDRPresentation Power Point Slides Video 29/10/12PDRPresentation Power Point Slides Video 5/12/12CDRPresentation Power Point Slides Video 10/12/12Final SDP Report WeeklyProject Status Meetings 13/2/13Progress Checkpoint #1Presentation and PPT Slides Alpha Schematic Alpha Board Layout Software Hierarchical Charts Test Matrix 5/3/13Final Design ReviewPresentation and PPT Slides 3/4/13Progress Checkpoint #2Final Schematics Final Board Layout Software Flow Charts Test Plan 15/5/13Progress Checkpoint #3Final Demonstration 20/5/13Final PresentationFinal Report Five Smart Plugs 15/6/13Integration with DSHField Test Plan 15/8/13DSH Integrated TestingField Test Report 15/9/13Final Acceptance

42. Questions/Comments 42