1. Lab 1: To generate layout for CMOS Inverter circuit and simulate it for verification.

2. VLSI Lab
References
I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments.
For further reading, I especially recommend the reference from Scientific American.
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 34

3. A complete VLSI lab set up should contain
Proper hardware
Proper software
Foundry or link up with some fab lab
Test facility
Purpose
References
I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments.
For further reading, I especially recommend the reference from Scientific American.
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 34

4. DESIGN STEPS SCHEMATIC LAYOUT DESIGN DRC LAYOUT Vs SCHEMATIC
PARASITIC EXTRACTION
POST LAYOUT SIMULTION
References
I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments.
For further reading, I especially recommend the reference from Scientific American.
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 34

5. List of Experiments
To generate layout for CMOS Inverter circuit and simulate it for verification.
To prepare layout for given logic function and verify it with simulations.
Introduction to programmable devices (FPGA, CPLD), Hardware Description Language (VHDL), and the use programming tool.
Implementation of basic logic gates and its testing.
Implementation of adder circuits and its testing.
Implementation of J-K and D Flip Flops and its testing.
Implementation 4 to 1 multiplexer and its testing.
Implementation of 3 to 8 decoder and its testing.
Implementation of sequential adder and its testing.
Implementation of BCD counter and its testing.
Simulation of CMOS Inverter using SPICE for transfer characteristic.
Simulation and verification of two input CMOS NOR gate using SPICE.
Introduction to Block Diagram Mathod
Design of digital Logic using block diagram.
References
I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments.
For further reading, I especially recommend the reference from Scientific American.
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 34

6. Project
Mini Project: VHDL/Verilog based mini project with emphasis on design and implementation into the group of maximum 3 students.
References
I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments.
For further reading, I especially recommend the reference from Scientific American.
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 34

7. Design Abstraction Levels+
DEVICE
CIRCUIT
GATE
MODULE
SYSTEM
References
I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments.
For further reading, I especially recommend the reference from Scientific American.
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 34

8. Microwind
Microwind is a tool for designing and simulating circuits at layout level. The tool features full editing facilities (copy, cut, past, duplicate, move), various views (MOS characteristics, 2D cross section, 3D process viewer), and an analog simulator
References
I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments.
For further reading, I especially recommend the reference from Scientific American.
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 34

9. Tools from Microwind Microwind DSCH Microwind3 Editor
Microwind 2D viewer
Microwind 3D viewer
Microwind analog simulator
Microwind tutorial on MOS devices
View of Silicon Atoms
References
I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments.
For further reading, I especially recommend the reference from Scientific American.
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 34

10. Getting Microwind Go to the website http://www.microwind.net/document
Download the freeware version of the microwind
Unzip the files in a Folder
References
I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments.
For further reading, I especially recommend the reference from Scientific American.
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 34

11. Microwind Downloads References
I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments.
For further reading, I especially recommend the reference from Scientific American.
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 34

12. INTRODUCTION THE TOOL
User-friendly and intuitive design tool for educational use.
The student draws the masks of the circuit layout and performs analog simulation
The tool displays the layout in 2D, static 3D and animated 3D
References
I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments.
For further reading, I especially recommend the reference from Scientific American.
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 34

13. Our Approach MOS DEVICE 1. 2. 3. 4. References
Traditional teaching : in-depth explanation of the potentials, fields, threshold voltage, and eventually the expression of the current Ids
Our approach : step-by-step illustration of the most important relationships between layout and performance.
Design of the MOS
I/V Simulation
2D view
Time domain analysis 1. 2. 3.
References
I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments.
For further reading, I especially recommend the reference from Scientific American. 4.
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 34

14. Feature Size Chips are specified with set of masks
Minimum dimensions of masks determine transistor size (and hence speed, cost, and power)
Feature size f = distance between source and drain
Set by minimum width of polysilicon
Feature size improves 30% every 3 years or so
Normalize for feature size when describing design Rules
E.g. λ = μm in μm process

15. Layout design rules:
For complex processes, it becomes difficult to understand the intricacies of the fabrication process and interpret different photo masks.
They act as interface between the circuit designer and the process engineer.

16. Microwind Environment
Menu Command
Editing Icons
Access to Simulation
One dot on the grid is 5 lambda or 0.30 µm
Layout Library
2D 3D Views
Simulation Properties
Palette of Layers
Work Area
Active Layers
Current Technology

17. Design Rules N- Well r101 Minimum width 12λ r102 Between wells 12 λ
r110 Minimum well Area 144 λ2
r 101
r 102
N - Well

18. r201 Minimum N+ and P+ diffusion width 4λ
N - Well
r 201
N+ Diff

19. r202 Between two P+ and N+ diffusions 4λ
P+ Diff
N - Well
r 202
N+ Diff

20. r203 Extra N-well after P+ diffusion 6λ
N+ Diff

21. r204 Between N+ diffusion and n-well 6 λ
P+ Diff
N - Well
r 204
N+ Diff

22. r210 Minimum diffusion area 16λ2
P+ Diff
N - Well
N+ Diff
r 210

23. r301 Polysilicon Width 2λ Polysilicon r 301 P+ Diff N - Well
N+ Diff

24. r302 Polysilicon gate on Diffusion 2λ
P+ Diff
N - Well
Polysilicon
r 302
N+ Diff

25. r307 Extra Polysilicon surrounding Diffusion 3λ
P+ Diff
r 307
N - Well
Polysilicon
r 307
N+ Diff
r 307

26. r304 Between two Polysilicon boxes 3λ
P+ Diff
N - Well
Polysilicon
r 304
N+ Diff

27. r307 Diffusion after Polysilicon 4λ
P+ Diff
N - Well
Polysilicon
r 307
r 307
N+ Diff

28. Metal/Polysilicon Contact
r401 Contact width 2λ
Contact
r 401
Polysilicon Contact
Metal/Polysilicon Contact

29. r404 Extra Poly surrounding contact 1λ
Polysilicon Contact
Metal/Polysilicon Contact

30. r405 Extra metal surrounding contact 1λ
Polysilicon Contact
Metal/Polysilicon Contact
r 405
r 405

31. r403 Extra diffusion surrounding contact 1λ
Polysilicon
r 403
P+ Diff
N - Well
Polysilicon
r 403
N+ Diff

32. r501 Between two Metals 4λ Metal 1 Metal 4 r 501 Metal 2 Metal 5 r 501

33. r510 Minimum Metal area 16λ2 Metal 1 Metal 4 r 510 r 510 Metal 2

34. Step 1: Select Foundary

35. Step 2: Select Foundary

36. Step 3: n+ Diffussion References
I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments.
For further reading, I especially recommend the reference from Scientific American.
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 34

37. Step 4: Polysilicon References
I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments.
For further reading, I especially recommend the reference from Scientific American.
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 34

38. Step 5: n+diff and Metal Contact
References
I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments.
For further reading, I especially recommend the reference from Scientific American.
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 34

39. This Completes nMOS design
Now go for pMOS Design, and the first need is to construct N Well
References
I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments.
For further reading, I especially recommend the reference from Scientific American.
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 34

40. Step 6: Create N Well References
I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments.
For further reading, I especially recommend the reference from Scientific American.
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 34

41. Step 6: p+ Diffusion References
I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments.
For further reading, I especially recommend the reference from Scientific American.
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 34

42. Step 7: Polysilicon References
I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments.
For further reading, I especially recommend the reference from Scientific American.
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 34

43. Step 8: Contacts References
I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments.
For further reading, I especially recommend the reference from Scientific American.
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 34

44. Final Connections pMOS Completed
Now Interconnection of pMOS and nMOS to complete inverter
Connect Source of pMOS to VDD and Source of nMOS to VSS.
Short the Drain of both pMOS and nMOS.
References
I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments.
For further reading, I especially recommend the reference from Scientific American.
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 34

45. INVERTER: Complete Design
References
I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments.
For further reading, I especially recommend the reference from Scientific American.
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 34

46. Check DRC
References
I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments.
For further reading, I especially recommend the reference from Scientific American.
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 34

47. Assign Source Assign Signal (Clock) to Gate Terminal
Add Visible node at Output
References
I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments.
For further reading, I especially recommend the reference from Scientific American.
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 34

48. Inverter with Source References
I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments.
For further reading, I especially recommend the reference from Scientific American.
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 34

49. Run Simulation References
I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments.
For further reading, I especially recommend the reference from Scientific American.
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 34

50. VTC Characteristics References
I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments.
For further reading, I especially recommend the reference from Scientific American.
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 34

51. Thanks Give Your Feedbacks at: www.amitdegada.weebly.com/blog.html
References
I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments.
For further reading, I especially recommend the reference from Scientific American.
Give Your Feedbacks at:
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 34

52. References
I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments.
For further reading, I especially recommend the reference from Scientific American.
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 34

53. References
I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments.
For further reading, I especially recommend the reference from Scientific American.
Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes 34