1. Inside The CPU

2. Buses There are 3 Types of Buses There are 3 Types of Buses Address bus Address bus –between CPU and Main Memory –Carries address of where data is supposed to go Data Bus Data Bus –between CPU and device (i.e. expansion bus) –Carries actual data Control Bus Control Bus –between CPU and device –Carries control information (i.e. is the device supposed to receive of send bits)

3. Registers Temporarily stores bits that the CPU will process Temporarily stores bits that the CPU will process Incredibly fast (speed of CPU) Incredibly fast (speed of CPU) Small number of registers Small number of registers Number of registers depends on manufacturer Number of registers depends on manufacturer Each register is specialized Each register is specialized A,B,C,D,E,H,L,PC,SP,SR A,B,C,D,E,H,L,PC,SP,SR

4. Step by Step Execution The CPU performs the fetch-decode-execute cycle The CPU performs the fetch-decode-execute cycle Fetch Fetch –gets the next instruction as indicated by the program counter (PC) and increment program counter Decode Decode –Decode the bit pattern in the IR (instruction register) Execute Execute –Perform the action requested in the IR

5. Larger CPUs Larger CPUs have components that will store code in the code cache and data in the data cache found in the Bus Interface Unit. Each component also has its own bus. Larger CPUs have components that will store code in the code cache and data in the data cache found in the Bus Interface Unit. Each component also has its own bus. The Instruction pre-fetch buffer and decode unit retrieves 256-bit bursts of data. It decides if it exchange between the ILU (integer and Logic Unit) or the FPU (floating point unit) The Instruction pre-fetch buffer and decode unit retrieves 256-bit bursts of data. It decides if it exchange between the ILU (integer and Logic Unit) or the FPU (floating point unit) There are 2 IALU (Integer ALU) There are 2 IALU (Integer ALU) FPU (floating point calculation unit) FPU (floating point calculation unit) BPU (branch prediction unit) BPU (branch prediction unit) –Organizes data that seems to go together such as loops or conditional statements

6. Clock Speeds Many of the fastest processors have speeds much slower than the processors found inside a desktop pc Many of the fastest processors have speeds much slower than the processors found inside a desktop pc BUS speed and BUS width controls the speed of RAM!!!! BUS speed and BUS width controls the speed of RAM!!!! 32-bit 2 GHZ computer operates at the same speed as a 16-bit 4 GHZ computer 32-bit 2 GHZ computer operates at the same speed as a 16-bit 4 GHZ computer Why? Do the calculation Why? Do the calculation What is the clock speed of a 128-bit 500 Mhz machine? What is the clock speed of a 128-bit 500 Mhz machine?

7. Latency Latency Latency –Time required to find the first memory address and transmit data –Makes the previous calculations purely theoretical. What’s the solution? Burst Mode and pipelining (a wide bus attaching the CPU and cache and several bytes are transferred simultaneously along the pipeline) Burst Mode and pipelining (a wide bus attaching the CPU and cache and several bytes are transferred simultaneously along the pipeline) Can you think of an analogy using highways and toll booths?

8. Instruction Cycle An instruction may type several clock ticks to complete An instruction may type several clock ticks to complete The computer continually has to do some housekeeping even is you are not using it The computer continually has to do some housekeeping even is you are not using it –Update screen –See if key has been pressed –Mouse location –Mouse clicks etc..

9. An instruction cycle (Stage 1) The CPU contains an address counter called the Program Counter (PC) The CPU contains an address counter called the Program Counter (PC) The PC contains the memory location of the next instruction along with the data for that instruction The PC contains the memory location of the next instruction along with the data for that instruction The address of the next instruction is placed on the address bus and is stored in memory The address of the next instruction is placed on the address bus and is stored in memory

10. An instruction cycle (Stage 2) Once the instruction and the data have been located this data is sent to the CPU along the data bus Once the instruction and the data have been located this data is sent to the CPU along the data bus

11. An instruction cycle (Stage 3) The PC is updated so it stores the address of the next instruction The PC is updated so it stores the address of the next instruction Goes to next one, two or three bytes for 8-bit data bus Goes to next one, two or three bytes for 8-bit data bus On next cycle PC is ready to tell CPU where to execute On next cycle PC is ready to tell CPU where to execute

12. An instruction cycle (Stage 4) CPU must execute the instruction retrieved in Stage 2 CPU must execute the instruction retrieved in Stage 2 The returned instruction is called an OP Code (Operation Code) The returned instruction is called an OP Code (Operation Code) Op Codes tell CPU what instruction to carry out Op Codes tell CPU what instruction to carry out CPU might already have loaded data (operands) which operations use CPU might already have loaded data (operands) which operations use

13. An instruction cycle (Stage 5) CPU is ready to carry out instruction CPU is ready to carry out instruction If a register is being updated, the required information is already available (remember stage 1: PC retrieves address location and data for next instruction) If a register is being updated, the required information is already available (remember stage 1: PC retrieves address location and data for next instruction) If instruction references another byte of memory (needs another operand), data needs to be received or written to If instruction references another byte of memory (needs another operand), data needs to be received or written to

14. An instruction cycle (Stage 6) Stage 1 is repeated Stage 1 is repeated The new address stored in the PC in stage 3 must be located and the whole process is repeated The new address stored in the PC in stage 3 must be located and the whole process is repeated

15. An instruction cycle (Stage 5) Last OP Code tells CPU the program is finished and the program will stop running Last OP Code tells CPU the program is finished and the program will stop running

16. What determines computer speed? Clock Speed Clock Speed CPU speed CPU speed Bus width Bus width Internal bus width (pipelining on large CPUs) Internal bus width (pipelining on large CPUs) LOOK at chart on page 177 comparing computer speeds from the past 30 years LOOK at chart on page 177 comparing computer speeds from the past 30 years

18. Memory Review How does CPU communicate with memory? How does CPU communicate with memory? What is the hierarchy of memory? What is the hierarchy of memory? What is swapping? What is swapping? What is thrashing? What is thrashing?