1. CMOS Analog Integrated Circuits: Models, Analysis, & Design EE448 MOS Circuit Level Models Fall 2001 Dr. John Choma, Jr. Professor of Electrical Engineering University of Southern California Department of Electrical Engineering-Electrophysics University Park; Mail Code: 0271 Los Angeles, California 90089-0271 213-740-4692 [OFF] 626-915-7503 [HOME] 626-915-0944 [FAX] johnc@almaak.usc.edu (E-MAIL)

2. Lecture Overview 2 Static Model  Cutoff Region  Ohmic (Triode) Region Model  Saturation Region Model  Subthreshold Model Short Channel Effects In Saturation  Channel Length Modulation  Substrate/Bulk Phenomena  Mobility Degradation  Carrier Velocity Saturation Small Signal Model In Saturation  Forward Transconductance  Bulk Transconductance  Capacitances Sample Circuit Analysis (Inverter)  Gain  Bandwidth

3. N–Channel MOSFET 3 I s =I d +I g +I b I g  0 I b  0, forV bs < 0 I s  I d V ds =V gs –V gd Silicon Dioxide B L T ox SDG N+ Source N+ Drain L d L d W X d P–Type Substrate (Concentration = N D cm -3 ) I d D G S V ds   B V bs   V gs   V gd   I g I s I b

4. P–Channel MOSFET 4 I s =I d +I g +I b I g  0 I b  0, forV sb < 0 I s  I d V sd =V sg –V dg D G S V sd   B V sb   V dg   I g I s I b I d V sg   Silicon Dioxide B L T ox SDG P+ Source P+ Drain L d L d W X d N–Type Substrate (Concentration = N D cm -3 )

5. Characteristic Curves: Cutoff And Ohmic Regimes l Cutoff Regime:   Threshold Voltage, Function Of Bulk–Source Voltage l Ohmic Regime:   (Hundreds Of µmhos/Volt) l Comments  W/L Is Gate–Channel Aspect Ratio, A Designable Parameter   Temperature Effects (Holes And Electrons):  Resistance For Small Drain–Source Voltage: 5 V hn  K n =µ n C ox = µ n  T µ(T)  µ(To)µ(To) T o T 3 / 2 V gs –V hn –V ds V gs –V hn – V ds 2 V gs  V hn and V ds <V gs –V hn  I d  V ds  1 R =K n W L V gs –V hn –V ds = I d V I d V 

6. Characteristic Curves: Saturated Regime l Saturation Regime:   l Comments  Square Law Voltage–Controlled Current Source  Drain Current Shows Negative Temperature Coefficient Because Of Its Proportionality To Mobility  Differential Current Of Two Matched Devices Is Linear With Differential Gate–Source Voltage, Provided Common Mode Gate–Source Voltage Is A Constant 6 V gs  V hn &V ds  V gs –V hn V dss  V gs –V hn  Drain Saturation Voltage I dss = K n 2 W L V 2  Drain Saturation Current

7. Simple Differential Pair 6a l Inputs l Response l Note Differential Output Current And Voltage Are Linear With Respect To Differential Input Voltage Without Invoking Small Signal Approximation

8. Characteristic Curves: Subthreshold Regime 7 l Subthreshold Regime: s l Comments s Bipolar Type I–V Action Indigenous To Subthreshold Regime s Subthreshold Operation Corresponds To Gate–Channel Interface Potentials Lying Between One And Two Fermi Potentials s Useful Only For Low Speed, Low Power Applications I d =2 K n W L n V T  2 e (V gs –V hn ) / n V T

9. Sample Simplified MOS Static Characteristics 8

10. l Depletion l Zero Current l l Voltage Across Oxide l Interface Potential V ds P–Type Substrate DEPLETION LAYER, V  0 ds SiO 2 I d SD G c  V gs   N+ Drain N+ Source DEPLETION LAYER, V= 0 ds B V bs  Fixed Immobile Charges V ds  0 0 <V gs <V hn V bs  0 V ox  V y  Cutoff Regime 9

11. Channel Inversion: Ohmic Regime 10 V gs >V hn 0  V ds  V gs –V hn V gd >V hn N+ Drain P–Type Substrate N+ Source N+ Drain P–Type Substrate N+ Source L L'DL DV ds Metal or Polysilicon Silicon Dioxide Inversion Layer Depletion DS G DS G V dss 

12. Channel Inversion: Saturation Regime 11 V gs >V hn 0  V ds =V gs –V hn V gd  V hn V gs >V hn 0  V ds >V gs –V hn V gd <V hn N+ Drain P–Type Substrate N+ Source N+ Drain P–Type Substrate N+ Source L L'  L  V ds Metal or Polysilicon Silicon Dioxide Inversion Layer Depletion DS G DS G V dss 

13. Channel Length Modulation l Modified Saturation Regime Current 12 I d | V ds >V dss =I L L –  L = K n 2 W L V gs –V hn 2 1 + V ds –V dss V V =L 2 q N A  s V ds –V dss +V j (Typically Under 20 Volts And As Small As 1/3 Volt For Deep Submicron MOSFETs) l Channel Modulation Voltage N+ Drain N+ Source L'DL  V ds DS G V dss 

14. Channel Length Modulation Parameters 13 l Parameters   Average Substrate Impurity Concentration   Dielectric Constant Of Silicon (1.05 pF/cm)   Electronic Charge Magnitude   Channel Length Modulation Voltage   Built In Substrate–Drain/Source Junction Potential l Note  Large Channel Length Reduces Channel Modulation  Small Substrate Concentration Increases Channel Modulation l Modified Saturation Regime Current I d | V ds >V dss =I L L –  L = K n 2 W L V gs –V hn 2 1 + V ds –V dss V V =L 2 q N A  s V ds –V dss +V j

15. Substrate/Bulk Phenomena l Effect On Threshold Voltage l Parameters   Fermi Potential; Renders Channel Surface Intrinsic   Intrinsic Carrier Concentration In Substrate   Dielectric Constant Of Silicon Dioxide (345 fF/cm) l Note  Small Oxide Thickness Reduces Threshold Modulation  Small Substrate Concentration Reduces Threshold Modulation 14    (High Hundreds Of µVolts)  (Few Tenths Of Volts)  ox I d = K n 2 W L V gs –V hnc 2 1 + V ds –V dss V V  = q N A  s C ox 2 =q N A  s T  2 V h =V ho +2 V  V F –V T 1 – V bs 2 V F –V T – 1

16. Threshold Voltage Modulation Threshold Correction (volts) Bulk–Source Voltage, Vbs (volts) 15

17. Mobility Degradation Due To Vertical Field 16 l Electric Field Problems  Thin Oxide Layers Conduce Large Gate -To- Channel Fields For Even Small -To- Moderate Gate–Source Voltages  These Enhanced Fields Impart Increasing Energies To Carriers, Thereby Causing More Carrier Collisions And Degraded Mobilities l Mobility: l Parameters   Effective Carrier Mobility In Channel   Vertical Field Degradation Voltage Parameter  Crude One Dimension Approximation To Two Dimensional Problem  in MKS Units Yields In Volts µ neff  µ n 1 + V gs –V hnc V E V E  (500)(10 6 ) T ox (Low Hundreds Of Volts)

18. Impact Of Mobility Degradation 17 l Static Drain Current  l Other Effects  Reduced Bandwidth And Increased Carrier Transit Time  Smaller Current For Given Gate–Source Bias  Reduced Forward Transconductance K n =µ n C ox  K neff =µ C ox I d = K n 2 W L V gs –V hnc 2 1 + V ds –V dss V 1 + V gs –V hnc V E

19. Mobility Degradation Due To Lateral Field 18 l Electric Field Problems  Short Channels Conduce Large Drain -To- Source Fields For Even Small -To- Moderate Drain–Source Voltages  These Enhanced Fields Impart Increasing Energies To Carriers, Thereby Causing More Carrier Collisions And Degraded Mobilities  At Very Large Horizontal Fields, Carrier Velocities Ultimately Saturate To A Value Of, Which Is About 0.1 µm/pSEC  Saturation Occurs When Horizontal Field,,Equals Or Exceeds A Critical Value,, Which Is About 5 V/µm l Mobility And Field  µ ne  µ n 1 + E h E c = v sat E c +E h v =µ ne E h  µ n E h 1 + E h E c E h  V gs –V hn L

20. Velocity – Mobility – Field Relationships 18a Lateral Electric Field (V/µm) 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 05101520253035404550 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Carrier Velocity (µm/psec)Normalized Carrier Mobility Carrier Velocity Normalized Mobility

21. Mobility And Lateral Field 19 l Mobility And Field  l Electric Field Problems  Crude Approximation For Horizontal Field,  Free Carriers Exist Only Over Channel Where Voltage With Respect To The Source Is At Most  Channel Length, L, Should Be Effective Channel Length, L', But This Shrinkage Is Already Accounted For By Channel Length Modulation Voltage Parameter,  Is About 1.75 Volts For L = 0.35 µm V E h  V gs –V hnc L = V dss L µ ne  µ n 1 + E h E c  µ n V gs –V hnc L E c = µ n 1 + V dss L E c

22. Volt–Ampere Impact Of High Lateral Field l Static Drain Current  l Very High Fields  l Comments  Drain Current Scales Approximately With W, As Opposed To W/L  Drain Current Almost Linear W/R To Gate–Source Voltage 20 K n =µ n C ox  K neff =µ C ox I d = K n 2 W L (V gs –V ) hnc 2 1 + V ds –V dss V 1 + V gs –V hnc L E c I d  W C ox v sat 2 V gs –V hnc 1 + V ds –V dss V l

23. MOS Large Signal Model  Gate-Drain Capacitance  Gate-Source Capacitance  Drain-Bulk Capacitance  Source-Bulk Capacitance  Drain Overlap Capacitance  Source Overlap Capacitance DBD  Bulk-Drain Diode DBS  Bulk-Source Diode 21  Drain Ohmic Resistance  Source Ohmic Resistance  Bulk Ohmic Resistance  Bulk Spreading Resistance Static Drain Current

24. Device Capacitances In Saturation 22  Drain-Bulk Junction Area  Source-Bulk Junction Area  Zero Bias Depletion Capacitance Density C gd +C old  C =W L d C ox  Large (Hundreds Of fF)  Moderate (High Tens Of fF)  Small (Tens Of fF)

25. Approximate (Long Channel) Small Signal Model 23 cc c c c B DG g mf v ga g o v ba +  v ga C old +  cc C gd c c g mb v ba C gs C db c C sb C ols c S l Assumptions  All Series Ohmic Resistances Are Negligible  Transistor Operates In Saturation Regime  "Long Channel" Approximation Invoked For Static Drain Current  Model To Be Used As A Precursor To Computer–Based Studies g mf   I d  V gs | Q  2 K n W L I dQ g mb   I d  V bs | Q = b g mf b = V  / 2 2 V F –V T –V bsQ g o   I d  V ds | Q  I dQ V +V ds –V dss

26. Short Channel Small Signal Model 24 l Drain Current: l Intermediate Parameters: l Forward Transconductance: l Bulk Transconductance: l Output Conductance: I d = K n 2 W L V gs –V hnc 2 1 + V ds –V dss V 1 + V gs –V hnc L E c f = V ds –V dss V g mfs =g mf 1 +f 1 +f c 1 – V dss / 2 V 1 +f – f c / 2 1 +f c g mbs = b g mfs g o = I dQ V +V ds –V dss b = V  / 2 2 V F –V T –V bsQ

27. Hypothetical Device 25 l Physical Parameters  s = 1.05 pF/cm  ox = 345 fF/cm l Device Parameters l Circuit Parameters

28. Static Performance l Peripheral Calculations 26 V hnc = 685.2 mV (Compensated Threshold)   V hn = 35.2 mV V = 669.7 mV (Channel Length Voltage) K n = 276.0 µmho / volt (Transconductance Parameter) f = 2.218 (Channel Length Parameter) l Static Drain Current   Note Short Channel -To- Long Channel Ratio of 2.35 ; Ratio Is Generally Between 1.5 And 3.0

29. Small Signal Parameters 27 l Forward Transconductance   Note Short Channel -To- Long Channel Ratio of 1.14 ; Ratio Is Generally Between 0.5 And 2.0 l Bulk Transconductance   Note Bulk Transconductance Is About 200 Times Smaller Than Forward Transconductance l Drain–Source Conductance   Corresponds To Shunt Output Resistance Of About 5 K   Mandates Conductance Enhancement Strategies When Designing High Performance Transconductors (10) –3 b = 5.02 (Bulk Parameter)

30. Device Unity Gain Frequency l l l Comments  Unity Gain Frequency Is Good Device Figure Of Merit; Crude Circuit Performance Figure Of Merit  Result Assumes  T C gd << g mf AC Short Circuit 28 i out i in = g mf –s C gd +C old s C gs +C ols +C gd +C old  T  g mf C gs +C ols +C gd +C old  µ n V gs –V hn L 2 2 3 + 3 L d L c c c BS D G g mf v 1 g mb v 2 g o v 2 +  v 1 +  c c V dd c I bias C big c i out i in i c i out C gd C old + C gs C ols +

31. Common Source Inverter 29

32. Inverter Load Resistance Calculations 30 R Leff  V x I x =r ssl + r ddl +r ol 1 + bl g mfl r ol  1 1 + bl g mfl

33. Inverter Gain Calculations 31 A v = V os V s = – g mfd R Leff 1 + bd g mfd r ssd + R Leff +r ddd +r ssd r od  – g mfd R Leff  – g mfd 1 + bl g mfl A v  – 1 1 + bl W d / L W l / L

34. Inverter Bandwidth Calculations 32 R / = V x I x =r ddd +r ssd + 1 + bl g mfd r ssd r od B 3dB  1 R Leff C L  1 + bl g mfl C L B 3dB = 1 R out C L = 1 R / | R Leff C L  1 R C L GBP  A v B 3dB = g mfd C L