1. Introduction to Basys 2

2. Switches Slide switchesPush button switches

3. Definition of Pin Number File: basys2.ucf Used during implementation stage LED outputs Slide switches Pushbutton switches The pin number of each

4. Software Adept Active HDL is used for writing Verilog code ISE/Webpack from Xilinx – Purpose: create a “bit” file from a Verilog file or schematic based source files – The “bit” file is used to configure the basys2 board before it can perform any useful functions. Adept can be used to configure the FPGA with any suitable bit file stored on the computer

5. Start Aldec Active-HDL Student Edition

6. Start a New Workspace

7. New Design Wizard

8. Synthesis/Implementation Paths We will use verilog in this class

9. Choose Default HDL Language to Verilog

10. Design Name

11. Set Paths for Integrated Tools

12. Design Entry

13. Verilog File

14. Keyword: module/endmodule The keywords module and endmodule encapsulate the text that describes the module

15. Comments A pair of slashes – // comment – Forms a comment from the text that follows it on the same line /* */ – /* comment */

16. Direction of the Signals The direction of the input and output signals is given by input, outout or inout (for a bi-directional signal) There are 6 outputs as an array Z[5:0]!

17. Schematic of Gates2

18. Concurrent Statements To describe the output each gate, we simply write the logic Equation for that gate preceded by the keyword assign. The concurrent statements are statements that can be written in any order.

19. wire You can think of a wire as a wire in a circuit where actual voltages Could be measured.

20. Compile

21. Simulate gates2.v

22. Create a Top-Level Test Bench You need to create a top-level test bench so you can use physical switches/push buttons to stimulate the design

23. Top-Level Verilog Test Bench

24. Top-Level Synthesis Option Input and output signals are assigned to pins on the FPGA during synthesis.

25. Synthesize

26. Error Message During Implementation Stage

27. Solution: incorrect Netlist

28. Implementation Completed with No Error

29. Adept Interface

30. Example 1

31. Example 2

32. Start Another Design

33. Use Push Buttons to control LED

34. Platform Flash Adept can also program a bit file into an on-board non-volatile ROM called “Platform Flash”. Once programmed, the Platform Flash can automatically transfer a stored bit file to the FPGA at a subsequent power-on or reset event if the Mode Jumper (JP3) is set to ROM. The FPGA will remain configured until it is reset by a power-cycle event. The Platform Flash ROM will retain a bit file until it is reprogrammed, regardless of power-cycle events.