1. 4 QFN Challenges that will Make you Scream!
Leadless Devices
4 QFN Challenges that will Make you Scream!
Background
2006 RoHS
Fast Forward we have more 0201s, stacked packages, leadless devices have replaced BGAs in terms of # of placements and lead free solder pastes are NOT going away
# 2 is Novemeber 1st from 1-2:30PM EST
BEST Inc.

2. Bottom Terminated Components The 4 “Biggies”
Void Reduction
Cleaning
Inspection
Rework

3. 1. Void Reduction Achieve Reliable Assembly with Minimal Voiding
Large area in thermal ground, lots of volume of flux, lots of outgassing
Voiding impedes thermal transfer, reducing the efficiency and lifetime of the package
No single approach has proven to be the solution
Important to reduce overall % voids and size of largest void
Try combinations of proven approaches to achieve the best possible process

4. Solder paste is ~50% flux by volume
Large paste deposit contains volatiles
During reflow volatiles must escape to accomplish complete coalescence
Low standoff leaves no exit for excess volatiles

5. Strategies to Reduce Voiding
Thermal pad and via design
Stencil design
Reflow profile optimization

6. Thermal Pad Design Considerations
Strategy: break up thermal pad to discourage large voids and facilitate venting
“Window paning” creates pathways to vent volatiles
Reduced pockets of volatiles cause smaller voids and less overall voiding
Downside: Vent channels result in less solder joint continuity

7. Split Thermal Pads
Split thermal pads reduce the size of voids, but do not significantly reduce the total voiding area
For thermal transfer, large voids are more disruptive -> smaller voids allow for more transfer
Solder mask defined pads offer further improvement
Dr. Lee et al. study this in “The Effect of Thermal Pad Patterning on QFN Voiding”

9. Dr. Lee et al. study this in “The Effect of Thermal Pad Patterning on QFN Voiding”

10. Voiding in QFN Unfilled Via-in-pad
This is why you must “seal” via-in-pad
This is why you must “seal” via-in-pad !

11. Voiding + Via in Pad Voiding even with Pad window Paning!
Note Voiding even with Pad window Paning! Also defects on pads
Excessive voids can also cause co-planarity issues and open QFN joints. IPC & JEDEC stipulates at least 50% coverage criteria for the thermal pad.
Voiding even with Pad window Paning!
Excessive voids can also cause co-planarity issues and open QFN joints
IPC & JEDEC stipulates at least 50% coverage criteria for the thermal pad. 11

12. Stencil Design
Instead of printing one large square at the center of QFNs:
With greater paste volume, voiding increases, so aperture designs that limit paste volume will reduce voiding
Break up this square into smaller apertures
Spaces between printed areas leave paths for volatiles to escape
“Influence of Reflow Profile and Pb-free Solder Paste in Minimizing Voids for QFN Assembly” by T. Jensen, E. Briggs et al.

13. Effects of Window Paning
Aperture reduction 50-60%
W Coleman; “Printing and Assembly Challenges for QFN Devices”; SMT Magazine, 4/11

14. Voiding vs. Stencil Thickness
Celestica in Thailand .4mm QFN on lg thick PWB
Additional DOE factors Reflow Profile+ Window Pane END
Songninluck, et al; “QUAD FLAT NO LEAD (QFN) PACKAGE PROCESSING IN HIGH THERMAL MASS ASSEMBLY”; SMTAI-10

15. Voiding vs. Window Pane “Focal Dot” 8mil spacing
NOTE SMALL Reduction!!! Celestica in Thailand .4mm QFN on lg thick PWB “Focal Dot” = Window Pane
Additional DOE factors Reflow Profile+ Stencil thickness
Window Pane can also minimize the “floating” phenomena causing slant/unbalance stand-off due to higher solder volume in the central pad relative to contact leads at the perimeter. END
Songninluck, et al; “QUAD FLAT NO LEAD (QFN) PACKAGE PROCESSING IN HIGH THERMAL MASS ASSEMBLY”; SMTAI-10

16. Reflow Profiling
There is no “magic” reflow profile to minimize voiding
For each assembly, the best profile will balance several requirements:
Thermal requirements of assembly
Optimal profile for the chosen solder paste
Requirements of other components (ie BGAs)
There will be an optimal profile, it may or may not minimize voiding
Profiling must be considered but not a solution

17. 2. Cleaning Underneath BTCs
Low clearance
Large center pad
High paste/flux volume
Difficult cleaning flow path

18. BTC: No-Clean Residue Issues
No-Clean: Solvents can’t escape => residue not safe (even though full time/temp exposure)
Flux volatilization is a critical factor with regard to the complexity of the flux residue so that it becomes benign
The fluxes are not benign until
they have seen enough heat to volatilize the solvents
create the insulative residue
this can only be done with enough heat and removal of the flux carrier

19. Courtesy of Foresite Inc

20. BTC No-Clean Residue Issue
In a no-clean process, when the flux is activated and fully volatilizes, it leaves a benign residue with no impact on field performance.
But when this solvent is not allowed to release:
Flux residue is conductive and moisture absorbing.
Product in the field for 9 months to still have gooey conductive flux causing performance problems.

21. BTC: No-Clean Residue Issues
No-Clean: Solvents can’t escape => residue not safe (even though full time/temp exposure)
Flux volatilization is a critical factor in the complexing of the flux residue so that it becomes benign. The fluxes are not benign until they have seen enough heat to volatilize the solvents and create the insulative residue and this only can be done with enough heat and removal of the flux carrier. In a no-clean process, when the flux is activated and fully volatilizes, it leaves a benign residue when the carrier or solvent has been released leaving a benign residue with no impact on field performance. But when this solvent is not
allowed to release then the flux residue is conductive and moisture absorbing. We have found product in the field for 9 months to still have gooey conductive flux causing performance problems.
T Munson; “ELECTRICAL LEAKAGE FAILURES DUE TO ENTRAPPED FLUX BELOW A QFN PACKAGE”; SMTAI-06

22. BTC Cleaning Need to have enough standoff distance (min’m 2.5mils)
Need to have pathways for the cleaning solutions to get enough impingement energy to the “soils”
Need to have enough kinetic energy to break soils free
Measure using ion chromatography

23. BTC Cleaning Study
Courtesy Zestron

24. Manual: Depends on wettable surface
3. Inspection
AOI: Pretty worthless
Manual: Depends on wettable surface
Endoscope (edge viewing optical microscope) reasonable for edge joints
X-Ray: good for voiding, bridges, wetting only method for central pad

25. IPC Inspection Criteria
I love it!! Dimension “B” is not allowed also not shown on drawing 25

26. Pullback vs. No-pullback
V Solberg; “ PCB Design Principles for QFN and Other Bottom Termination Components”; APEX-11

27. Metallization-easier inspection

28. Shadowing; Solder Balls
Consider AOI trying to evaluate this component?

29. Multiple pads different AOI Algorithms

30. More Defects; CT Scan
Bastin & Krastev; “QFN PROCESS CONTROL VIA 2D AND 3D CT X-RAY INSPECTION TECHNIQUES “; SMTAI-11

31. High Yield, Simple and Fast
4. Rework
High Yield, Simple and Fast
IPC

32. Rework Technique
IPC

33. Rework Technique
IPC

34. Part Bumping Using a Polyimide Peel-n-Stick Stencil(s)
IPC
Step #1
Align and apply stencil to device. Roll solder paste through apertures.

35. Part Bumping Using a Polyimide Peel-n-Stick Stencil(s)
Step #2
Reflow per solder mfr’s profile recommendations

36. Part Bumping Using a Polyimide Peel-n-Stick Stencil(s)
Step #3
Remove stencil and clean. Surface now is “bumped”

37. Part Bumping Using a Polyimide Peel-n-Stick Stencil(s)
Inspection of “bumped” device

38. Part Bumping Using a Polyimide Peel-n-Stick Stencil(s)
Step #4
Prep land area on PCB where device is to be placed

39. Part Bumping Using a Polyimide Peel-n-Stick Stencil(s)
Step #5
Align and adhere board stencil on PCB. Roll solder paste into apertures and clean off residue.

40. Part Bumping Using a Polyimide Peel-n-Stick Stencil(s)
Step #6
Place “bumped” QFN into stencil apertures. Feel the “bumps” fit into the apertures

41. Part Bumping Using a Polyimide Peel-n-Stick Stencil(s)
Step #7
Reflow as per solder paste manufacturers’ profile recommendations. Perform visual inspection. Perform X-ray inspection.

42. Print Quality

43. Print Reliability

44. BEST Inc.