1. EE 319K Introduction to Embedded Systems
Lecture 15: Final Exam Review
Valvano class competition will be Thursday PHR 2.108
Superfinals Friday 3-4 ECJ1.202
Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

2. Final Exam Final exam will be similar in style to Exam 1
Approximately the same length and format as previous final exams
You will have three hours if you need it
Comprehensive, good things to study are
All the lecture notes & worksheets posted
All lab work
Textbook (sections listed in syllabus)
All homework
Zyante book (specified in HW)
All prior exams (finals and Exam 1s)
Time entire test alone; review solutions with friends
Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

3. Final Exam Any technical documents required will be provided
Closed book, closed notes
No calculators allowed (all calculations will be simple)
Partial credit for answers in equation form
It may have short answer questions
Conversions, definitions
Will have longer questions involving assembly and C
Local variables, FSM, interrupts, ADC input, DAC
Focus will be on fundamentals and techniques
You should be able to do software problems in both assembly and C!
Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

4. Final Exam Review Definitions (matching or multiple choice)
volatile, nonvolatile, RAM, ROM, port, kibibyte, mebibyte
static efficiency, dynamic efficiency, white box, black box
structured program, call graph, data flow graph
basis, nibble, precision, decimal digits, promotion, demotion
fixed-point, overflow, ceiling and floor, drop out
desk check, intrusive, dump, stabilization, profile, heartbeat
bus, address bus, data bus, bus cycle
memory-mapped, I/O mapped, vector, device driver,
Von Neumann architecture, Harvard architecture, CISC, RISC
tristate, open collector, ALU, registers
negative logic, positive logic, Ohm’s Law, P=V*I, KVL, KCL
thread, real-time, latency, interrupt, vector, priority
private, public, local, global, call by value, call by reference
friendly, mask, toggle, baud rate, bandwidth, frame
Nyquist Theorem, monotonic, accuracy, jitter
ADC/DAC limits: max, min, resolution, fs, number of samples
PLL (tradeoff between power and speed)
Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

5. Final Exam Review Number conversions - convert one format to another
decimal digits
signed decimal e.g., -56
unsigned decimal e.g., 200
binary e.g., %
hexadecimal e.g., 0xC8
IEEE 754 floating point (not this semester)
Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

6. Final Exam Review Instruction detail and Cortex-M operation
operation of ARM instructions (reference sheet)
components in address space
subroutine linkage
stack operations
8-bit addition, subtraction yielding result, N, Z, V, C
No N Z V C this semester
Simple programs
create global variables
specify an I/O pin is an input
specify an I/O pin is an output
clear an I/O output pin to zero
set an I/O output pin to one
toggle an I/O output pin
check if an I/O input pin is high or low
add, sub, shift left, shift right, and, or, eor
Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

7. Final Exam Review Switch & LED interfacing GPIO Ports SysTick Timer
friendly programming practices
LED and switch interfacing
bit-specific addressing (no bit-specific addressing this year)
SysTick Timer
initialization
operational parameters
period
busy-wait delay or periodic interrupt
Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

8. Final Exam Review System Design Finite State Machines Local Variables
Successive Refinement, modularity
Stepwise Refinement
Systematic Decomposition
Finite State Machines
Moore and Mealy machine characteristics
abstraction
programming structures
Local Variables
types of storage
stack, registers, binding, SP address, stack frame addressing
C programming
Variables, expressions, control, data structures
casting and indirection, pointers, arrays, structures
storage type qualifiers
const static volatile
Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

9. Final Exam Review I/O Synchronization Interrupts
Purpose, types
blind cycle, busy/wait, interrupt, DMA
Semaphore, mailbox, FIFO
Device Driver
Performing I/O with an external device (like the LCD)
Interrupts
initialization rituals
software actions/what needs to be done
interrupt service routines
hardware operation
thread context switch/what needs to be done
debugging techniques
Mailbox and FIFO queues
operation
programming
But simpler
Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

10. Final Exam Review Digital To Analog Converter (DAC) Sound Generation
Operation, characteristics, Ohm’s Law
Sound Generation
Discrete time sinusoid
Periodic interrupts
Timing requirements
Analog To Digital Converter (ADC)
Operation, characteristics, programming
Nyquist Theorem
UART
Operation, programming, start bit, stop bit, rates
Real time and communication systems
Latency, jitter, throughput ≡ bandwidth
Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

11. Practice Problems in Book
Hardware interfacing
4.12, 4.13, 4.15, 4.17
Parallel Port initialization
4.5, 4.6, 4.7, 4.10, 4.11
Software
4.18, 4.19, 4.20, Lab 4.3, Lab 4.5, Lab 4.6,
5.1, 5.2, 5.3, 5.4, 5.5, 5.6, 5.7, 5.8, 5.9, 5.10
Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

12. Practice Problems in Book
Pointers
6.1, 6.2, 6.3, 6.4, 6.6, 6.7, 6.9,
Matrix (2-D array)
6.10, 6.11,
FSM
6.12, 6.13, 6.14, 6.15
Variables
7.1, 7.2, 7.3, 7.4,
Parameters
7.5, 7.15, 7.16, 7.18
Fixed point
7.6, 7.7, 7.10, 7.11, 7.12, 7.13, 7.22
Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

13. Practice Problems in Book
Recursion
7.21
UART
8.1, 8.2, 8.3, 11.10, 11.11
SysTick, interrupts
9.1, 9.4, 9.7, 9.8, 9.10, 9.12, 9.15, 9.16
DAC
10.1
Checkpoints
ADC
Checkpoint 10.8
FIFO
Checkpoints
Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

14. Comp Architecture/Embedded Systems
Digital Logic
Introduction to
Design
Microcontrollers
(EE 316 | FS)
(EE 319K | FS)
Embedded
Digital
Computer
Systems Lab
System Design
Architecture
Algorithms
(EE 460M | FS)
(EE 445L | FS)
(EE 460N | FS)
(EE 360C | FS)
Electives
Real-Time
Computer-Aided
and Embedded
Concurrent and
IC Design
Systems
Distributed
(EE 445M | S)
Systems
(EE 460R | FS)
(EE 360P | S)
Real-Time
DSP
Laboratory
(EE 445S | FS)
Operating Systems (EE379K)
From small To large systems
Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

15. Comp Architecture/Embedded Systems
Required
EE Digital Logic Design
EE 460N Computer Architecture
EE 445L Embedded Systems Lab
EE 360C Algorithms
M 325K Discrete Mathematics
Three of the following
EE 422C Software Design and Implementation II
EE 445M Embedded and Real-Time Systems Lab
EE 445S Real-Time Digital Signal Processing Lab
EE 460M Digital Systems Design Using VHDL
EE 360P Concurrent and Distributed Systems
EE 460R Computer-Aided Integrated Circuit Design
EE 362K Introduction to Automatic Control
CS Compilers (Fall 2016 ECE course as well)
EE 379K New OS course, Fall 2015
Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

16. Computer System Design
Understanding the operation and design of computers
Applications,
Operating systems,
Compilers,
Instruction set,
Microarchitecture,
Logic design,
Circuit design
Good secondary cores: Electronics and IC, Software
Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

17. We’ve Come a Long Way Transistor count doubles every 18 months
But Moore’s Law is merely describing a device-level phenomenon. How do you use the ever more abundant transistor to build more power microprocessors?
I’m going to explain a few
Transistor count doubles every 18 months
Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

18. Computer Architecture Area
Design of general-purpose computer systems
From personal (laptops, desktops) to cloud (servers)
Which courses are most relevant & important?
EE 460N for computer architecture
What are important technical challenges today?
Size, speed, security, software/hardware, power
What industries/companies need these skills?
Any company making computer equipment
How do I prepare for graduate school?
Take EE 460N Comp. Arch. and EE 360C Algorithms
Get involved in undergraduate research
MS degree is essential for this area
Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

19. Embedded Systems Area Design of special-purpose computer systems
From toasters (μController) to airplanes (systems-on-chip)
Which courses are most relevant & important?
EE445L digital-analog codesign, systems level design
EE445M real-time operating systems, device drivers, and autonomous robots
What are important technical challenges today?
Time-to-market; maximizing use of Moore’s law
Size, power, profit margins
What industries/companies need these skills?
Any company making super high volume products
How do I prepare for graduate school?
Take EE 460N Comp. Arch. and EE 360C Algorithms
Get involved in undergraduate research
Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

20. EE460N Computer Arch What is Architecture, Tradeoffs
Instruction Set Architecture, LC-3b ISA
Assemblers: Translating Assembly Language to ISA
Microarchitecture: Detailed LC-3b implementation
Physical memory, unaligned access, interleaving, SRAM, DRAM
Virtual memory, page tables, TLB, VAX model, PowerPC model, contrast with segmentation
Cache memory
Interrupts/Exceptions
I/O
Performance Improvement. Metrics, Pipelining.
Branch prediction
Out-of-order execution
Vector processing
Integer arithmetic, Floating point, IEEE Standard
Measurement Methodology
Intro to Multiprocessing, Interconnection networks, Amdahl's Law, Consistency models
Cache coherency
Alternative Models of Concurrency: SIMD, MIMD, VLIW, dataflow, etc.
State-of-the-art Microprocessor
Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

21. EE460N - Labs Write an assembler Write an instruction set simulator
Write a cycle-level simulator
Interrupt support
Virtual memory
Pipeline
Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

22. EE460M Digital Design Using VHDL
Review of Basic Logic Design Techniques (with emphasis on timing)
Design Flow, High Level Design
VHDL Descriptions of Digital Systems and Simulation
Synthesis
Design using Programmable Logic Devices
SM Charts
Field Programmable Gate Arrays (FPGAs)
Advanced Topics in VHDL
Test Generation and Design for Testability
Rapid Prototyping using FPGAs
Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

23. EE460M - Labs VHDL’s timing to model gate-level circuits
FSM simulation
VHDL Package Sorter
Traffic Meter Simulation
BCD conversion, Square Root
Microprocessor Design & Implementation in FPGA
VGA Graphics and Keyboard Interface
Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

24. EE445L Embedded Systems Lab
debugging with an oscilloscope and a logic analyzer;
design of an alarm clock and I/O driver;
design of a real-time data acquisition system;
Motor control;
design of a music player, DAC, data structure design;
Power management and PCB layout;
Wireless communication, layered protocol;
board-level design, construction and testing of a complete embedded system
Friday 1pm ECJ lab
Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

25. EE445L - Labs Lab 1. ASCII to fixed-point output to OLED
Lab 2. Debugging, oscilloscope, logic analyzer, dump
Lab 3. Alarm clock, edge-triggered input interrupts
Lab 4. Stepper motor, interrupts, finite state machine
Lab bit DAC, SPI, Music player, audio amp
Lab 6. Introduction to PCB Layout, PCB Artist
Lab 7. Design and Layout of an Embedded System
Lab 8. Software Drivers for an Embedded System
Lab 9. Measurement, ADC, analog amp
Lab 10. Wifi, UART, distributed systems
Lab 11. Evaluation of Embedded System
Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

26. EE445M Real-time operating systems
Lab 1. I/O port drivers
Lab 2. Real-time operating system kernel
Lab 3. Blocking semaphores, priority
Lab 4. Microphone input, digital filters, FFT,
Lab 5. Solid state disk, SSI, address translation, layered software, file system
Lab 6. Distributed acquisition using Ethernet
Lab 7 Formula 0001 Racing Robot
Go watch the races in Spring
Tue/Thur 5pm ECJ court yard
Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

27. For more information Bard, Bill (network communications)
Chase, Craig (software design)
Chiou, Derek (architecture)
Erez, Mattan (architecture)
Evans, Brian L. (DSP applications)
Gerstlauer, Andreas (embedded systems, IC)
Janapa Reddi, Vijay (architecture)
John, Lizy (architecture)
Patt, Yale (architecture)
Swartzlander, Earl (architecture)
Tiwari, Mohit (architecture, security)
Valvano, Jonathan (embedded medical devices)
Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi