1. Methods to Differentiate Mil/Aero Solutions Using FPGAs BOF session W – Focus on verification Dan Gardner Final MAPLD BOF Presentation

2. Gardner MAPLD 2005/P145_BOF-W 2 Requirements for FPGA Software in Mil/Aero n Cost effective delivery of mission performance — Initial Creation n Cost and speed of design — Predictable time to market at fixed cost — Fast iterations — Timing and system closure — Complete Verification n Commercial FPGA often skips many verification steps n Some Mil/Aero applications have additional considerations — Maintenance of Project n Cost of life cycle maintainability of design n Support of standard platforms n Support Mil-preferred devices, documentation and flows

3. Gardner MAPLD 2005/P145_BOF-W 3 Technologies to Consider n All technologies listed below are required to build a complete methodology and will be covered n This presentation will essentially focus on the unique requirements of Mil/Aero FPGA applications: — Rule checker with platform-independent coding styles — Design management — RTL + physical synthesis — I/O design with integration path to PCB — System-level design — Verification n Electronic System-Level (ESL) Overview n Assertion based (CDC to validate SEU protection) n Coverage driven n Clock domain crossing (CDC) — Embedded systems

4. Gardner MAPLD 2005/P145_BOF-W 4 Verification Technology n Rule checker with platform-independent coding styles n Design management n Verification — Electronic System-Level (ESL) Overview — Assertion based (CDC to validate SEU protection) — Coverage driven — Clock domain crossing (CDC) n Embedded systems

5. Gardner MAPLD 2005/P145_BOF-W 5 Rule Checkers n n Encapsulate knowledge: – – Expect built-in checks from standard sources – – Reuse Methodology Manual – – FPGA vendor recommendations – – Must allow quick customization for your own checks n n Use Early and Often: — — Perform checking interactively or in batch — — Understand the causes of violations — — Easily interact, organize, & track violations — — Interactively trace & fix violations n n Share knowledge: — — Share checks with the team/company — — Allow any designer to apply accumulated knowledge — — Export results for reporting Static Design Checking for VHDL/Verilog RTL

6. Gardner MAPLD 2005/P145_BOF-W 6 : HDL Designer: Manage Text, Graphics, VHDL, Verilog, SystemC, SystemVerilog, PSL, C/C++, Scripts, Revision Control, Automated Design Documentation Rule Checking & Project Management Process Automation Version Management SynthesizeSynthesize Design / Document PCB – I/O Designer VerificationVerification

7. Gardner MAPLD 2005/P145_BOF-W 7 Verification Technology n Rule checker with platform-independent coding styles n Design management n Verification — Electronic System-Level (ESL) Overview — Assertion based (CDC to validate SEU protection) — Coverage driven — Clock domain crossing (CDC) n Embedded systems

8. Gardner MAPLD 2005/P145_BOF-W 8 Language Design Languages & Tasks Task Requirements AlgorithmExploration ArchitectureAnalysis Verification RTL Design Text / UML TransactionLevelSystemC VHDLVerilog HVLs extend & accelerate the RTL design process and enable RTL designers to cross the chasm to system level design AssertionsPSL/SVA SystemVerilog C/C++UntimedSystemC

9. Gardner MAPLD 2005/P145_BOF-W 9 Abstraction Drives Design Productivity RTLRTL Algorithmic C++ Untimed TLM SystemC Timed TLM SystemC Cycle Accurate SystemC Simulation Source Implementation 1x (7 days) 10,000x (1 min) 10x 100x 1,000x 1x (5 weeks) 20x (2 days!!) 2x (2 weeks) Functional Structural Cycle RTL Transaction

10. Gardner MAPLD 2005/P145_BOF-W 10 Automatic Generation of Verification Infrastructure ComparatorComparator Golden resultsDUT results Original C++ Algorithm Algorithm RTLRTL TransactorTransactor TransactorTransactor n n Facilitates the verification of the synthesized design n n The original C++ testbench can be reused to verify the design — — RTL or cycle accurate — — SystemC, VHDL or Verilog n n Transactors convert function calls to pin-level signal activity n n Pushbutton verification solution includes Makefiles and simulation scripts Original C++ Testbench Testbench

11. Gardner MAPLD 2005/P145_BOF-W 11 Exhaustive Algorithm Verification With Automated Real Time Prototypes n Quickly produce RTL code from algorithmic specifications — Regardless of the quality of the architecture n Run RTL synthesis and P&R with integrated tool flows n Validate the functional correctness of the algorithm on FPGA prototyping boards — Architecture optimization can be pursued in parallel Algorithms Precision RTL Synthesis Catapult C Synthesis FPGA Vendor P&R Prototyping ? Netlist Constraints C Code Constraints RTL Code Constraints

12. Gardner MAPLD 2005/P145_BOF-W 12 Hardware ASIC/FPGA Place & Route RTL Synthesis Fixed Point C++ Model Floating Point Model Catapult C Synthesis Constraints + Logic Analyzer Algorithm Functional Description n n Safer design flow n n Shorter time to RTL n n More efficient methodology n n Design optimized to system requirements through incremental refinement Catapult C Addresses the ESL Synthesis Challenge Floating Point Model Fixed Point Model Micro-architecture Definition RTL Design RTL Area/Timing Optimization RTL Synthesis Place & Route Hardware ASIC/FPGA Manual Methods Logic Analyzer + MATLAB SPW C/C++ Precision RTL or DC ASIC or FPGA Vendor Algorithm Functional Description System Designer Hardware Designer Vendor Typical RTL Design Flow NEW Catapult C Design Flow

13. Gardner MAPLD 2005/P145_BOF-W 13 Methodology Explosion Targeting Verification n Assertion-based verification n Functional coverage n Constrained-random testing n Coverage-driven verification n Dynamic-formal verification n Transaction-level verification n Model checking n And more...

14. Gardner MAPLD 2005/P145_BOF-W 14 Common Verification Methodologies

15. Gardner MAPLD 2005/P145_BOF-W 15 SystemVerilog for Verification n SystemVerilog is a complete Verification Language — Can be used with VHDL — Stimulus generation capabilities n Dynamically configurable constrained-random value generation n Ability to generate constrained-random stimulus sequences n Ability to randomly select control paths (test scenario selection, etc.) — Functional coverage modeling n Measure the verification quality and test effectiveness n Dynamic reactivity with constrained-random stimulus generation — Assertion-based verification n Property specification n Assertion & coverage monitoring — High-level modeling (programming) capabilities n Efficiently and effectively model the operational environment n Develop reusable verification environments

16. Gardner MAPLD 2005/P145_BOF-W 16 Reference Model Assertion Checkers Bus Monitor Assertion Checkers Bus Monitor Assertion-Based Verification Assertions Enable Higher Quality Designs n Assertions provide observability for higher complexity designs — ABV makes assertions a key element, ensuring that design properties are not violated n Assertions describe (un)desired behavior n Assertions dramatically shorten debug and repair time n Assertions stay on during block, chip and system-level tests — Finds bugs you weren’t looking for

17. Gardner MAPLD 2005/P145_BOF-W 17 Expect Widespread Use of Coverage-Driven Verification n PSL and SystemVerilog provide coverage constructs n Simulators integrating functional coverage to improve performance and debug n New test strategies require functional coverage — Random and constrained random tests need coverage to determine what they tested

18. Gardner MAPLD 2005/P145_BOF-W 18 Clock-Domain Crossings n Incorrect handling of Clock-Domain Crossing (CDC) signals is the 2nd major cause of re-spins n Traditional verification techniques do not work for CDC signals n CDC problems are subtle, will occur in hardware, and are complex to debug Assertion Synthesis automates CDC verification, significantly reducing the risk of CDC-related silicon re-spins Assertion Synthesis automates CDC verification, significantly reducing the risk of CDC-related silicon re-spins

19. Gardner MAPLD 2005/P145_BOF-W 19 Complete Verification Flow Assertion Based Verification Language: SVA and/or PSL Engine: Questa-AFV IP: CheckWare Automation: Assertion Synthesis

20. Gardner MAPLD 2005/P145_BOF-W 20 Verification Technology n Rule checker with platform-independent coding styles n Design management n Verification — Electronic System-Level (ESL) Overview — Assertion based (CDC to validate SEU protection) — Coverage Driven — Clock domain crossing (CDC) n Embedded systems

21. Gardner MAPLD 2005/P145_BOF-W 21 ASAPPlatform Exp Platform FPGAs Need a Complete Flow ISE Tools Chipscope SW-HW OnChip Debug XRAYNucleus Inventra Precision Synthesis Modelsim Platform Studio IDE Seamless ISS Microtec BSP Code|Lab Stacks Software Hardware PCB, Signal Integrity Tools

22. Gardner MAPLD 2005/P145_BOF-W 22 HW/SW Co-verification: Faster Iteration Loop n Supports: Edit/Compile/Verify n Eliminates: Edit/Synthesize/ Implement/Download/Verify n Promotes: Superior Visibility and Control HDL Entry Synthesis Implementation Download Bitstream Into FPGA Evaluation Board HDL Entry HDL Compile Seamless FPGA Co-Verification Without Co-verification With Co-verification

23. Gardner MAPLD 2005/P145_BOF-W 23 Summary n With engineers from software, hardware and system disciplines all converging on FPGAs, it is important to focus on the methods that can help differentiate your solution from others. n It is necessary to use all the basic verification and design tools, but there are new technologies emerging that can better address the unique requirements of Mil/Aero applications.