1. Design and Synthesis of a RISC Stored-Program Machine
Using Verilog HDL
Prepared by: Engr. Qazi Zia , Assistant Professor EED, COMSATS Attock

2. Design and Synthesis of a RISC Stored-Program Machine
Lecture 14-15
Design and Synthesis of a RISC Stored-Program Machine
Prepared by: Engr. Qazi Zia , Assistant Professor EED, COMSATS Attock

3. What is RISC
RISC (reduced instruction set computer) is a machine that has
A small set of instructions
Each instruction is executed in short clock cycles (small number of cycles per instruction)
Prepared by: Engr. Qazi Zia , Assistant Professor EED, COMSATS Attock

4. Prepared by: Engr. Qazi Zia , Assistant Professor EED, COMSATS Attock

5. Main Components The machine consists of Processor (datapath)
Controller (Control Unit )
Memory
Prepared by: Engr. Qazi Zia , Assistant Professor EED, COMSATS Attock

6. . IR: contains instruction that is to be executed
Program instructions and data are stored in memory. In program-directed operation, instructions are fetched synchronously from memory, decoded and executed to
Operate on data within the ALU
Change the contents of storage registers
Change the contents of the PC, IR and address register (ADD_R)
Change the contents of memory
Retrieve data and instructions from memory
Control the movement of data on the system busses
PC: contains address of next instruction that is to be executed
ADD_R: contains address of memory location that will be addressed next by a read or write operation
Prepared by: Engr. Qazi Zia , Assistant Professor EED, COMSATS Attock

7. RISC SPM: Processor
An Instruction can be fetched from memory, placed on Bus_2, loaded into the IR
The processor includes:
Registers
Data paths
Control signals
ALU
A word of data can be fetched from memory, placed on Bus_2, loaded into a general purpose register or to the operand register (Reg_Y) prior to the operation of ALU
The result of an ALU operation can be placed on Bus_2, loaded into a register , and also transferred to memory
Prepared by: Engr. Qazi Zia , Assistant Professor EED, COMSATS Attock

8. ALU The ALU has two operand datapaths data_1 and data_2
The ALU instructions are:
Prepared by: Engr. Qazi Zia , Assistant Professor EED, COMSATS Attock

9. The controller
All time-based activities of the machine are controlled by the controller.
The control unit does the following tasks:
Determines when to load registers
Selects the path of data through the multiplexers
Determines when data should be written to memory
Controls the three-state busses
Prepared by: Engr. Qazi Zia , Assistant Professor EED, COMSATS Attock

10. CU The signals produced by the controller are:
Prepared by: Engr. Qazi Zia , Assistant Professor EED, COMSATS Attock

11. The Instruction Set
The machine is controlled by a set of instructions stored in memory
The format of an instruction may be short or long depending on the operation.
The short instruction is of 8bits first 4 bits is opcode and the remaining 2 , 2 bits are the addresses of the source and destination registers.
The long instruction is of 16bits. In first byte, first 4 bits is opcode and the remaining 2 , 2 bits are the addresses of the source and destination registers. The 2nd byte is the memory address.
Prepared by: Engr. Qazi Zia , Assistant Professor EED, COMSATS Attock

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15. Controller Design
The machine cycle is further divided into fetch, decode and execute cycles.
Fetch: retrieving an instruction from memory. It takes two clock cycles- one to load the address register and one to retrieve the addressed word from memory.
Decode: decoding instruction, manipulating datapaths and loading registers. It takes one CC.
Execute: Generating the result of an instruction. It may require zero, one, two or more CCs depending on the instruction. NOT inst. Can execute in the same CC that the inst. is decoded.
Prepared by: Engr. Qazi Zia , Assistant Professor EED, COMSATS Attock

16. execute
Single byte instructions are executed in one CC e.g. ADD instruction is executed in single CC in which the result is loaded to destination register.
Two byte instructions take 2 CCs
e.g. RD – one to load address reg with 2nd byte
and one to retrieve word from memory addressed by 2nd byte and to load it into the destination register.
Prepared by: Engr. Qazi Zia , Assistant Professor EED, COMSATS Attock

17. 11 States of the controller
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30. Control Unit code
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36. Memory unit
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