1. Computers Central Processor Unit

3. Basic Computer System MAIN MEMORY ALUCNTL..... BUS CONTROLLER Processor I/O moduleInterconnections BUS Memory

5. Computer Components Processing (CPU) Arithmetic Logic Unit Control Unit Registers Word Clock Instruction sets Interconnection Local bus Peripheral bus Primary Storage RAM/ROM Cache Input/Output Channel Controller Buffers

6. CPU’s

7. Inside the CPU Registers

8. Instruction Cycle Fetch Processor locates the next instruction and loads it into the Instruction Register Execute Processor carries out the instruction currently in the Instruction Register Increment the program counter

9. CPU Cycle Start FETCHEXECUTE Halt Increment Program Counter FETCHEXECUTE

10. Instruction Format Instruction: Operation Codes Operands Word: set of bits held by registers in the CPU. May contain instructions or data. OP CodeOperands 4 Bits 12 Bits

11. Assembler & Machine Code

12. Example Assembler Code Fragment L(940) Load the contents of 940 A(941) Add the contents of 941 to the accumulator S(941) Store the accumulator to address 941 ADD numbers in location #940 and #941 STORE them in memory location #941.

13. Initial State IR 300PC CONTROL ARITHMETIC-LOGIC ACCUM PROGRAM 1940 5941 2941 300 301 302 DATA 0003 0002 940 941

14. CPU Registers: User-visible Data Registers User defined: data values to be used by the program Address Registers Index register: for relative address base Segment pointer (s): for op. System & other apps Stack pointer: for base of the stack Condition codes (flags)

15. CPU Registers: Control and Status Execution Program counter: Address of next instruction to be fetched Instruction Register: content of instruction most recently fetched Memory Access Memory Address Register: address in memory for next put or fetch Memory Buffer Register: data for next put or last fetch I/O Processing I/O Address Register: “ I/O Buffer Register: “

16. Initial State IR 300PC CONTROL ARITHMETIC-LOGIC ACCUM PROGRAM 1940 5941 2941 300 301 302 DATA 0003 0002 940 941

17. L(940) Load the contents of 940: Fetch IR 300PC CONTROL ARITHMETIC-LOGIC ACCUM PROGRAM 1940 5941 2941 300 301 302 DATA 0003 0002 940 941 1940

18. IR 300PC CONTROL ARITHMETIC-LOGIC ACCUM PROGRAM 1940 5941 2941 300 301 302 1 DATA 0003 0002 940 941 L(940) Load the contents of 940: Execute 3

19. 940IR 300PC CONTROL ARITHMETIC-LOGIC 3ACCUM PROGRAM 1940 5941 2941 300 301 302 1 DATA 0003 0002 940 941 L(940) Load the contents of 940: Increment 301

20. A(941) Add the contents of 941 to the accumulator Fetch IR 301PC CONTROL ARITHMETIC-LOGIC 3ACCUM PROGRAM 1940 5941 2941 300 301 302 DATA 0003 0002 940 941 5

21. IR 301PC CONTROL ARITHMETIC-LOGIC 3ACCUM PROGRAM 1940 5941 2941 300 301 302 5 DATA 0003 0002 940 941 A(941) Add the contents of 941 to the accumulator Execute 5

22. 941IR 301PC CONTROL ARITHMETIC-LOGIC 5ACCUM PROGRAM 1940 5941 2941 300 301 302 5 DATA 0003 0002 940 941 A(941) Add the contents of 941 to the accumulator Increment 302

23. S(941) Store the accumulator to address 941 Fetch IR 302PC CONTROL ARITHMETIC-LOGIC 5ACCUM PROGRAM 1940 5941 2941 300 301 302 DATA 0003 0002 940 941 2

24. IR 302PC CONTROL ARITHMETIC-LOGIC 5ACCUM PROGRAM 1940 5941 2941 300 301 302 2 DATA 0003 0002 940 941 S(941) Store the accumulator to address 941 Execute 0005

25. Instructions Instructions are broken into parts for operation codes and for addresses The length of the word dictates how many choices there are of each one More extensive instructions may require either multi-word reads or the use of external subroutines

26. Binary Representations

27. Limits 4 bit operation code implies 16 instructions (not all defined) 12 bit address space gives a maximum of 4096 addressable locations in memory 16 bits allow for (15 + sign) data representation bits

28. Uses for Instructions Data Movement: transfer data to or from memory or peripheral device Data Transformation: Boolean instructions (NOT, AND, OR, XOR) Arithmetic Operations: ADD, SHIFT Sequence Control: alter the sequence of instructions (BRANCH, JUMP)

29. Instruction Format Instruction: Operation Codes Operands Word: set of bits held by registers in the CPU. May contain instructions or data. OP CodeOperands 4 Bits 12 Bits

30. Types of Instructions Chip Instructions = Built-in Machine Instructions – “microcode” = Chip Instructions + ROM Instructions Assembler Instructions =Alphabetic Abbreviations for Machine Instructions

31. ROM Instructions ALUCNTL..... ROM INSTRUCTIONS (BIOS in PCs)

32. Assembler & Machine Code Machine code and assembler code are the same except that machine code uses the binary representations Assembler requires managing memory and registers directly Machine language (assembler) activates chip instructions and microcode instructions stored on ROM

33. Assembler & Machine Code

34. Complex Instructions L(940) Load the contents of 940 A(941) Add the contents of 941 to the accumulator S(941) Store the accumulator to address 941 = ADD(940, 941) Add the content of location 940 to that in 941 and store in 941.

35. RISC and CISC CISC uses fewer processor cycles RISC has fewer instructions, requires more processor cycles How can RISC be faster?

36. Clock Rate zSystem timing pulse frequency zMeasured in hertz (HZ) – cycles per second zCycle time = 1/clock rate zDon’t confuse with instruction execution rate (MIPS, MFLOPS)

37. Word Size Amount of data CPU processes at one time How much faster is a 64-bit processor than a 32-bit? What’s the ratio of associated computer components?

38. The Physical CPU Tubes -> transistors -> integrated circuits-> microchips Microprocessors All circuits and connections needed to implement a CPU

39. Chip capacity doubles every 18 Months. And a corollary… Rock’s Law – The cost of fabrication doubles every four years Gordon Moore Moore’s Law

40. Moore’s Law in Action © 2000 Intel Corporation

41. Computer Theory Mathematical foundations of computing Turing Machines Von Neumann Architecture

42. Turing Machines Theoretical model of a computer developed by Alan M. Turing in 1930’s. Basis for theoretical analysis of languages and machine complexity

43. Turing Machine Infinite Tape The tape is divided into squares any of which can contain a tape symbol. Initially the tape contains a string of input symbols in the beginning cells and blanks in the others Tape Head Reads or writes tape symbols Finite Control limited # of possible internal states One instruction = One change of state.

44. Turing Machine FINITE CONTROL TAPE aaaa BBBB STATE

45. Turing Machine Operation Current configuration consists of (current state, the non-blank tape symbols, current cell number) Next Move Function MOVE(current state, tape symbol) = (new symbol, new state, move left/right)

46. Turing Machine Operations Change State Prints a non-blank symbol on the tape replacing what was there Moves right or left one cell A function is computable if it can be computed by a Turing machine!

47. Components of a Turing Machine States Tape Symbols Tape Input Program Functions Start State Final State Register contents Character set Memory Program Chip Instruction Built in start Termination condition TURING MACHINE COMPUTER

48. Von Neumann Architecture: Stored Program Machine CPU Fast Memory Slow Storage Binary Program: executed in sequence Computer behavior is determined by stored programs.

49. John Von Neumann and ENIAC