1. Christoph Höhne Michael Kaufmann

2.  Motivation  Super Scalar Architecture  Implementation Details  Annoying Hazards  Comparisons  Conclusion

3.  Take advantage of possible parallelism on instruction level  Better utilization of components  Less hardware overhead than multiple scalar CPU-cores

4. IF ID EX MEM WB Cache Regfile ALU Memory

5. IF ID EX WB Cache Regfile ALU MEM ALU MUL ALU MUL BR RS

6. Block-RAM (32x32 Bit) Block-RAM (32x32 Bit) DI1 DI2 DO1.adr DI1.adr DO1 DO2 Block-RAM (32x32 Bit) Block-RAM (32x32 Bit) DO3 DO4 CLK 2x DO2.adr DO3.adr DO4.adr DI2.adr

7. IF ID EX WB Cache Regfile ALU MEM ALU MUL ALU MUL BR RS Add $1, $2, $3 Mul $4, $5, $6 $2, $3 $8, $9 $1 $4 Sub $6, $2, $3 Sub $7, $8, $9 $1 $7

8. ALU MEM MUL ALU MUL ALU BR ADD MUL ADD ST JMP MUL CALL MUL JZ JMP ST LD ADD BR ST ADD

9. ALUMULBRLS ALU MUL ✗✗ BR ✗✗ LS ✗✗ structural_hazards <= active_high((std_match(instr_even.instr.ir(Ropcode),MUL)and std_match(instr_odd.instr.ir(Ropcode),MUL)) or (std_match(instr_even.instr.ir(Ropcode),MUL)and std_match(instr_odd.instr.ir(Ropcode),BRNOP)) or (std_match(instr_even.instr.ir(Ropcode),BRNOP )and std_match(instr_odd.instr.ir(Ropcode),MUL)) or (std_match(instr_even.instr.ir(Ropcode),BRNOP )and std_match(instr_odd.instr.ir(Ropcode),BRNOP )) or (std_match(instr_even.instr.ir(Ropcode),BRNOP )and std_match(instr_odd.instr.ir(Ropcode),LS )) or (std_match(instr_even.instr.ir(Ropcode),LS )and std_match(instr_odd.instr.ir(Ropcode),LS ))); odd even

10. IF ID EX WB Cache Regfile ALU MEM ALU MUL ALU MUL BR RS Mul $1, $2, $3 Mul $4, $5, $6 $2, $3 $5, $6 $1 $4

11.  Read-After-Write Hazard (RAW)  Instruction requires operand which has not yet been written.  Solution: Forwarding  Write-After-Write Hazard (WAW)  Same target register for concurrent issued instructions.  Solution: Stalling

12. IF ID EX WB Cache Regfile ALU MEM ALU MUL ALU MUL BR RS Mul $1, $2, $3 Add$1, $1, $4 $2, $3 $1, $4 $1

15.  Literature != Practice  Timing is hell  MUXes need a lot of time and cannot be simply avoided  Wiring needs a lot of time  DLL clock doubling  Latches are evil in synthesis  Incomplete sensitivity list costs hours  Optimization sometimes leads to unexpected results

16. Questions?

17. IF ID EX WB Cache Regfile ALU MEM ALU MUL ALU MUL BR RS Add $1, $2, $3 Mul $4, $5, $6 Sub $1, $2, $3 Ls $4, $5, $6 Mul $1, $2, $3 Mul $4, $5, $6