1. Shunt-Peaking (1)
By connecting an inductor in series with the load resistor (series connection in shunt with output), more current is used, for a longer time, to charge the load capacitance.
As distinct from series peaking, shunt peaking places inductor in series with load resistor (shunting CL).
Idea behind this technique is that L opposes current change in R branch, allowing more time for C to charge with full current.
EECS 270C / Winter 2013
Prof. M. Green / U.C. Irvine

2. Properties of Shunt-Peaking
Frequency response: CL
Insertion of shunt-peaking inductor introduces a zero, partially cancelling the existing pole, and a higher-frequency pole, thus broadbanding the circuit.
Even though there is an inductor, it is not a frequency-selective circuit; thus resonance is not desired here.
Resonant frequency: X
Re s
Im s
L = 0:
pole at s = −1/RC X O
L ≠ 0:
zero at s = −R/L
additional pole at
s ≈ −(1/CR + R/L)
No resonance for
EECS 270C / Winter 2013
Prof. M. Green / U.C. Irvine

3. Shunt-Peaking -- AC Response
BW = 6.3 GHz
L = 1.8 nH
BW = 9.4 GHz
L = 3.7 nH
BW = 14.3 GHz
Use of shunt-peaking
increases small-signal bandwidth
EECS 270C / Winter 2013
Prof. M. Green / U.C. Irvine

4. Shunt Peaking − Transient Response (1)
Step Response:
td = 13.4 ps
L = 1.8 nH
td = 8.5 ps
L = 3.7 nH
td = 6.7 ps
Pulse Response (Dtin = 50 ps):
L = 3.7 nH
Dtout = 50.8 ps
ISI = 16 mUI
L = 1.8 nH
Dtout = 50.0 ps
ISI = 0 mUI
L = 0
Dtout = 48.7 ps
ISI = 26 mUI
EECS 270C / Winter 2013
Prof. M. Green / U.C. Irvine

5. Other Advantages of Shunt-Peaking
CML load is passive & linear
Can be shown to be very robust in the presence of parasitic series resistance and shunt capacitance  inductors can be placed far away from other CML circuit elements.
EECS 270C / Winter 2013
Prof. M. Green / U.C. Irvine

6. Effect of Shunt-Peaking Inductor Parasitics (1)L L L CP CP L
long metal lines RP RP R R R R CL CL CL CL
Series resistance RP simply adds to R
Shunt capacitance CP resonates with L …
EECS 270C / Winter 2013
Prof. M. Green / U.C. Irvine

7. Effect of Shunt-Peaking Inductor Parasitics (2)
ISI (UI) vs. input pulse width
Moderate amount of parasitic capacitance
has similar effect to slightly larger inductor.
ISI (UI) vs. input pulse width
Disadvantages of using passive inductors:
Consume huge die area
Difficult to design & model
EECS 270C / Winter 2013
Prof. M. Green / U.C. Irvine

8. Multi-layer Inductors (1)
metal 6
metal 6 d
metal 5
metal 5 d
Distance d between two metal layers is much smaller than lateral distances (e.g., w, l, s)
EECS 270C / Winter 2013
Prof. M. Green / U.C. Irvine

9. Multi-layer Inductors (2)
2-port representation of coupled inductors:
series connection of coupled inductors: L1 L2 i1 i2 M 1 + _ 2 i1 i2 + + 1 L1 L2 2 _ _
Passivity constraint:
For metal geometries close to each other,
k is close to unity.
For L1 = L2 = L, we have:
In general, for n layers we have:
Multi-layer inductors are more appropriate for shunt-peaking than resonant structures due to additional contact resistance.
EECS 270C / Winter 2013
Prof. M. Green / U.C. Irvine

10. Multi-layer Inductors (3)
Effective Capacitance: Ci Cj
For more details, see:
A. Zolfaghari, A. Chan & B. Razavi, “Stacked inductors and transformers in CMOS technology,”
IEEE Journal of Solid-State Circuits, vol. 36, April 2001, pp
EECS 270C / Winter 2013
Prof. M. Green / U.C. Irvine

11. Multi-layer Inductors (4)
Area comparison:
metal 6 over metal 4
46 x 46
w = 4; s = 2; n = 2.5
L=2.0 nH
R=12.5 
metal 6 only
100 x 100
w = 4; s = 2; n = 4
L=2.0 nH
R=6.9  +
EECS 270C / Winter 2013
Prof. M. Green / U.C. Irvine

12. Active Inductors (1) Rgyr Rgyr i1 i2 iin v1 v2 vin C
Impedance inversion:
Ideal gyrator:
Rgyr
Rgyr i1 i2
iin + + + v1 v2
vin C _ _ _
Matrix representation (Z-parameters):
Port 1 exhibits inductance when
port 2 is connected to a capacitance.
EECS 270C / Winter 2013
Prof. M. Green / U.C. Irvine

13. Active Inductors (2) Consider common-drain configuration: RG
i1 applied with port 2 open-circuited: i2
i2 applied with port 1 open-circuited: + RG v2 _ _
(Assume RG gm > 1) v1 i1 +
Complete Z-parameters (lossy/active gyrator):
EECS 270C / Winter 2013
Prof. M. Green / U.C. Irvine

14. Active Inductors (3) vin Interpretation of non-ideal matrix entries: +_
vin
EECS 270C / Winter 2013
Prof. M. Green / U.C. Irvine

15. Active Inductors (4) At low frequencies (Cgs open)  Zsource = 1/gm
Impedance at port 1 with port 2 terminated with transistor Cgs:
At low frequencies (Cgs open)  Zsource = 1/gm
At high frequencies (Cgs short)  Zsource = RG
EECS 270C / Winter 2013
Prof. M. Green / U.C. Irvine

16. Active Inductors (5) vin + _ Equivalent circuit:
EECS 270C / Winter 2013
Prof. M. Green / U.C. Irvine

17. CML Buffer with Active Inductor Load
Low-frequency gain:
For shunt peaking:
EECS 270C / Winter 2013
Prof. M. Green / U.C. Irvine

18. Active Inductor AC Response
RG = 4k
RG = 2k
RG = 0
EECS 270C / Winter 2013
Prof. M. Green / U.C. Irvine

19. Active Inductor Transient Response (1)
Differential signals:
RG = 0
PW = 97ps
RG = 5k
PW = 100 ps
RG = 10k
PW = 104 ps
EECS 270C / Winter 2013
Prof. M. Green / U.C. Irvine

20. Active Inductor Transient Response (2)
Single-ended signals:
Problem: n-channel load shifts output by Vt.
Vsb > 0; body effects exacerbates this effect..
Single-ended
input
Single-ended
outputs
EECS 270C / Winter 2013
Prof. M. Green / U.C. Irvine

21. Active Inductor Alternate Topology
p-channel load exhibits lower Vt
(Vbs = 0)
differential
single-ended
EECS 270C / Winter 2013
Prof. M. Green / U.C. Irvine